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| author | Jonas Gorski <jogo@openwrt.org> | 2013-04-28 11:10:42 +0000 |
|---|---|---|
| committer | Jonas Gorski <jogo@openwrt.org> | 2013-04-28 11:10:42 +0000 |
| commit | a33dd13c98772202be29835d93d70ae41c72f600 (patch) | |
| tree | 35de5b238a6c4ed26e3505500ee8322c6e47cfaa /target/linux/generic/patches-3.9 | |
| parent | 6a2dd833cf45b38dbef679b38032b6ad00d0d9b3 (diff) | |
| download | mtk-20170518-a33dd13c98772202be29835d93d70ae41c72f600.zip mtk-20170518-a33dd13c98772202be29835d93d70ae41c72f600.tar.gz mtk-20170518-a33dd13c98772202be29835d93d70ae41c72f600.tar.bz2 | |
kernel: add missing bcma defines and header file for bcrmfmac
Fixes build failure when having kmod-mmc and brcmfmac selected.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 36468
Diffstat (limited to 'target/linux/generic/patches-3.9')
| -rw-r--r-- | target/linux/generic/patches-3.9/025-bcma_backport.patch | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/target/linux/generic/patches-3.9/025-bcma_backport.patch b/target/linux/generic/patches-3.9/025-bcma_backport.patch new file mode 100644 index 0000000..489dc20 --- /dev/null +++ b/target/linux/generic/patches-3.9/025-bcma_backport.patch @@ -0,0 +1,32 @@ +--- a/include/linux/bcma/bcma.h ++++ b/include/linux/bcma/bcma.h +@@ -134,6 +134,7 @@ struct bcma_host_ops { + #define BCMA_CORE_I2S 0x834 + #define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */ + #define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */ ++#define BCMA_CORE_ARM_CR4 0x83e + #define BCMA_CORE_DEFAULT 0xFFF + + #define BCMA_MAX_NR_CORES 16 +--- a/include/linux/bcma/bcma_regs.h ++++ b/include/linux/bcma/bcma_regs.h +@@ -37,6 +37,7 @@ + #define BCMA_IOST_BIST_DONE 0x8000 + #define BCMA_RESET_CTL 0x0800 + #define BCMA_RESET_CTL_RESET 0x0001 ++#define BCMA_RESET_ST 0x0804 + + /* BCMA PCI config space registers. */ + #define BCMA_PCI_PMCSR 0x44 +--- a/include/linux/bcma/bcma_driver_chipcommon.h ++++ b/include/linux/bcma/bcma_driver_chipcommon.h +@@ -316,6 +316,9 @@ + #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */ + #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */ + #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16 ++#define BCMA_CC_PMU_CTL_RES 0x00006000 /* reset control mask */ ++#define BCMA_CC_PMU_CTL_RES_SHIFT 13 ++#define BCMA_CC_PMU_CTL_RES_RELOAD 0x2 /* reload POR values */ + #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400 + #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */ + #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */ |