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| author | Luka Perkov <luka@openwrt.org> | 2013-10-03 13:06:42 +0000 |
|---|---|---|
| committer | Luka Perkov <luka@openwrt.org> | 2013-10-03 13:06:42 +0000 |
| commit | 60dd4429b71227cbecf22892b26e125fedd4159d (patch) | |
| tree | a2fd41a346c7726c17f980ae49a6e74216a33741 /target/linux/imx6/patches-3.10/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch | |
| parent | 5617993e1059509ab09b1f3f210634c1f6a48af8 (diff) | |
| download | mtk-20170518-60dd4429b71227cbecf22892b26e125fedd4159d.zip mtk-20170518-60dd4429b71227cbecf22892b26e125fedd4159d.tar.gz mtk-20170518-60dd4429b71227cbecf22892b26e125fedd4159d.tar.bz2 | |
imx6: update upstream pcie patches
Signed-off-by: Luka Perkov <luka@openwrt.org>
SVN-Revision: 38298
Diffstat (limited to 'target/linux/imx6/patches-3.10/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch')
| -rw-r--r-- | target/linux/imx6/patches-3.10/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/target/linux/imx6/patches-3.10/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch b/target/linux/imx6/patches-3.10/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch new file mode 100644 index 0000000..19ca079 --- /dev/null +++ b/target/linux/imx6/patches-3.10/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch @@ -0,0 +1,37 @@ +From: Sean Cross <xobs@kosagi.com> +Subject: [PATCH 1/2] ARM: imx6q: Add PCIe bits to GPR syscon definition + +PCIe requires additional bits be defined for GPR8 and GPR12. + +Signed-off-by: Sean Cross <xobs@kosagi.com> +Signed-off-by: Shawn Guo <shawn.guo@linaro.org> +Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> +--- + include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h ++++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +@@ -241,6 +241,12 @@ + + #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) + ++#define IMX6Q_GPR8_TX_SWING_LOW (0x7f << 25) ++#define IMX6Q_GPR8_TX_SWING_FULL (0x7f << 18) ++#define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB (0x3f << 12) ++#define IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB (0x3f << 6) ++#define IMX6Q_GPR8_TX_DEEMPH_GEN1 (0x3f << 0) ++ + #define IMX6Q_GPR9_TZASC2_BYP BIT(1) + #define IMX6Q_GPR9_TZASC1_BYP BIT(0) + +@@ -273,7 +279,9 @@ + #define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26) + #define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25) + #define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24) ++#define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12) + #define IMX6Q_GPR12_PCIE_CTL_2 BIT(10) ++#define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4) + + #define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30) + #define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29) |