ipq806x: Add support for IPQ806x chip family

Patches are generated using the "format-patch" command from the
following location:
*https://www.codeaurora.org/cgit/quic/kernel/galak-msm/log/?h=apq_ipq_base
*rev=0771849495b4128cac2faf7d49c85c729fc48b20
Patches numbered 76/77/102/103 have already been integrated in 3.14.12,
so they're not in this list.

All these patches are either integrated are pending integration into
kernel.org, therefore these patches should go away once the kernel
gets upgraded to 3.16.

Support is currently limited to AP148 board but can be extended to other
platforms in the future.

These changes do not cover ethernet connectivity.

Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>

SVN-Revision: 42334

1 files changed, 70 insertions, 0 deletions

diff --git a/target/linux/ipq806x/patches/0010-devicetree-bindings-Document-Krait-Scorpion-cpus-and.patch b/target/linux/ipq806x/patches/0010-devicetree-bindings-Document-Krait-Scorpion-cpus-and.patch
new file mode 100644
index 0000000..0bcd3e8
--- /dev/null
+++ b/target/linux/ipq806x/patches/0010-devicetree-bindings-Document-Krait-Scorpion-cpus-and.patch
@@ -0,0 +1,70 @@
+From 236d07c7bb0c758ea40ea0110d37306d2e7d9a4b Mon Sep 17 00:00:00 2001
+From: Rohit Vaswani <rvaswani@codeaurora.org>
+Date: Thu, 31 Oct 2013 17:26:33 -0700
+Subject: [PATCH 010/182] devicetree: bindings: Document Krait/Scorpion cpus
+ and enable-method
+
+Scorpion and Krait don't use the spin-table enable-method.
+Instead they rely on mmio register accesses to enable power and
+clocks to bring CPUs out of reset. Document their enable-methods.
+
+Cc: <devicetree@vger.kernel.org>
+Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
+[sboyd: Split off into separate patch, renamed methods to
+match compatible nodes]
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Signed-off-by: Kumar Gala <galak@codeaurora.org>
+---
+ Documentation/devicetree/bindings/arm/cpus.txt |   25 +++++++++++++++++++++++-
+ 1 file changed, 24 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
+index 9130435..333f4ae 100644
+--- a/Documentation/devicetree/bindings/arm/cpus.txt
++++ b/Documentation/devicetree/bindings/arm/cpus.txt
+@@ -180,7 +180,11 @@ nodes to be present and contain the properties described below.
+ 			  be one of:
+ 			     "spin-table"
+ 			     "psci"
+-			# On ARM 32-bit systems this property is optional.
++			# On ARM 32-bit systems this property is optional and
++			  can be one of:
++			    "qcom,gcc-msm8660"
++			    "qcom,kpss-acc-v1"
++			    "qcom,kpss-acc-v2"
+ 
+ 	- cpu-release-addr
+ 		Usage: required for systems that have an "enable-method"
+@@ -191,6 +195,21 @@ nodes to be present and contain the properties described below.
+ 			  property identifying a 64-bit zero-initialised
+ 			  memory location.
+ 
++	- qcom,saw
++		Usage: required for systems that have an "enable-method"
++		       property value of "qcom,kpss-acc-v1" or
++		       "qcom,kpss-acc-v2"
++		Value type: <phandle>
++		Definition: Specifies the SAW[1] node associated with this CPU.
++
++	- qcom,acc
++		Usage: required for systems that have an "enable-method"
++		       property value of "qcom,kpss-acc-v1" or
++		       "qcom,kpss-acc-v2"
++		Value type: <phandle>
++		Definition: Specifies the ACC[2] node associated with this CPU.
++
++
+ Example 1 (dual-cluster big.LITTLE system 32-bit):
+ 
+ 	cpus {
+@@ -382,3 +401,7 @@ cpus {
+ 		cpu-release-addr = <0 0x20000000>;
+ 	};
+ };
++
++--
++[1] arm/msm/qcom,saw2.txt
++[2] arm/msm/qcom,kpss-acc.txt
+-- 
+1.7.10.4
+