* adds spi driver, thx daniel

SVN-Revision: 26355

4 files changed, 1218 insertions, 0 deletions

diff --git a/target/linux/lantiq/patches/940-spi1.patch b/target/linux/lantiq/patches/940-spi1.patch
new file mode 100644
index 0000000..343db3d
--- /dev/null
+++ b/target/linux/lantiq/patches/940-spi1.patch
@@ -0,0 +1,44 @@
+From: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
+Date: Thu, 3 Mar 2011 17:15:58 +0000 (+0100)
+Subject: MIPS: lantiq: Add platform data for Lantiq SoC SPI controller driver
+X-Git-Url: http://nbd.name/gitweb.cgi?p=lantiq.git;a=commitdiff_plain;h=3d21b04682ae8eb1c1965aba39d1796e8c5ad84b;hp=06b420500fe98e37662837e78d8e51aead8aea81
+
+MIPS: lantiq: Add platform data for Lantiq SoC SPI controller driver
+
+Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
+---
+
+--- a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
++++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
+@@ -48,4 +48,13 @@
+ 
+ extern int (*lqpci_plat_dev_init)(struct pci_dev *dev);
+ 
++
++struct lq_spi_platform_data {
++	u16 num_chipselect;
++};
++
++struct lq_spi_controller_data {
++	unsigned gpio;
++};
++
+ #endif
+--- a/arch/mips/include/asm/mach-lantiq/xway/xway.h
++++ b/arch/mips/include/asm/mach-lantiq/xway/xway.h
+@@ -72,6 +72,7 @@
+ #define LQ_PMU_BASE_ADDR	(KSEG1 + 0x1F102000)
+ 
+ #define PMU_DMA				0x0020
++#define PMU_SPI				0x0100
+ #define PMU_USB				0x8041
+ #define PMU_LED				0x0800
+ #define PMU_GPT				0x1000
+@@ -105,6 +106,7 @@
+ 
+ /*------------ SSC */
+ #define LQ_SSC_BASE_ADDR	(KSEG1 + 0x1e100800)
++#define LQ_SSC_SIZE		0x100
+ 
+ /*------------ MEI */
+ #define LQ_MEI_BASE_ADDR	(KSEG1 + 0x1E116000)
diff --git a/target/linux/lantiq/patches/941-spi2.patch b/target/linux/lantiq/patches/941-spi2.patch
new file mode 100644
index 0000000..9cc23a1
--- /dev/null
+++ b/target/linux/lantiq/patches/941-spi2.patch
@@ -0,0 +1,1103 @@
+From: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
+Date: Thu, 3 Mar 2011 17:15:30 +0000 (+0100)
+Subject: SPI: lantiq: Add driver for Lantiq SoC SPI controller
+X-Git-Url: http://nbd.name/gitweb.cgi?p=lantiq.git;a=commitdiff_plain;h=653c95b8b9066c9c6ac08bd64d0ceee439e9fd90;hp=3d21b04682ae8eb1c1965aba39d1796e8c5ad84b
+
+SPI: lantiq: Add driver for Lantiq SoC SPI controller
+
+Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
+---
+
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -176,6 +176,14 @@
+ 	  This enables using the Freescale i.MX SPI controllers in master
+ 	  mode.
+ 
++config SPI_LANTIQ
++	tristate "Lantiq SoC SPI controller"
++	depends on SOC_LANTIQ_XWAY
++	select SPI_BITBANG
++	help
++	  This driver supports the Lantiq SoC SPI controller in master
++	  mode.
++
+ config SPI_LM70_LLP
+ 	tristate "Parallel port adapter for LM70 eval board (DEVELOPMENT)"
+ 	depends on PARPORT && EXPERIMENTAL
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -24,6 +24,7 @@
+ obj-$(CONFIG_SPI_GPIO)			+= spi_gpio.o
+ obj-$(CONFIG_SPI_GPIO_OLD)		+= spi_gpio_old.o
+ obj-$(CONFIG_SPI_IMX)			+= spi_imx.o
++obj-$(CONFIG_SPI_LANTIQ)		+= spi_lantiq.o
+ obj-$(CONFIG_SPI_LM70_LLP)		+= spi_lm70llp.o
+ obj-$(CONFIG_SPI_PXA2XX)		+= pxa2xx_spi.o
+ obj-$(CONFIG_SPI_OMAP_UWIRE)		+= omap_uwire.o
+--- /dev/null
++++ b/drivers/spi/spi_lantiq.c
+@@ -0,0 +1,1063 @@
++/*
++ * Lantiq SoC SPI controller
++ *
++ * Copyright (C) 2011 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
++ *
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/workqueue.h>
++#include <linux/platform_device.h>
++#include <linux/io.h>
++#include <linux/sched.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/completion.h>
++#include <linux/spinlock.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/gpio.h>
++#include <linux/spi/spi.h>
++#include <linux/spi/spi_bitbang.h>
++
++#include <xway.h>
++#include <xway_irq.h>
++#include <lantiq_platform.h>
++
++#define LQ_SPI_CLC		0x00	/* Clock control */
++#define LQ_SPI_PISEL		0x04	/* Port input select */
++#define LQ_SPI_ID		0x08	/* Identification */
++#define LQ_SPI_CON		0x10	/* Control */
++#define LQ_SPI_STAT		0x14	/* Status */
++#define LQ_SPI_WHBSTATE	0x18	/* Write HW modified state */
++#define LQ_SPI_TB		0x20	/* Transmit buffer */
++#define LQ_SPI_RB		0x24	/* Receive buffer */
++#define LQ_SPI_RXFCON		0x30	/* Receive FIFO control */
++#define LQ_SPI_TXFCON		0x34	/* Transmit FIFO control */
++#define LQ_SPI_FSTAT		0x38	/* FIFO status */
++#define LQ_SPI_BRT		0x40	/* Baudrate timer */
++#define LQ_SPI_BRSTAT		0x44	/* Baudrate timer status */
++#define LQ_SPI_SFCON		0x60	/* Serial frame control */
++#define LQ_SPI_SFSTAT		0x64	/* Serial frame status */
++#define LQ_SPI_GPOCON		0x70	/* General purpose output control */
++#define LQ_SPI_GPOSTAT		0x74	/* General purpose output status */
++#define LQ_SPI_FGPO		0x78	/* Forced general purpose output */
++#define LQ_SPI_RXREQ		0x80	/* Receive request */
++#define LQ_SPI_RXCNT		0x84	/* Receive count */
++#define LQ_SPI_DMACON		0xEC	/* DMA control */
++#define LQ_SPI_IRNEN		0xF4	/* Interrupt node enable */
++#define LQ_SPI_IRNICR		0xF8	/* Interrupt node interrupt capture */
++#define LQ_SPI_IRNCR		0xFC	/* Interrupt node control */
++
++#define LQ_SPI_CLC_SMC_SHIFT	16	/* Clock divider for sleep mode */
++#define LQ_SPI_CLC_SMC_MASK	0xFF
++#define LQ_SPI_CLC_RMC_SHIFT	8	/* Clock divider for normal run mode */
++#define LQ_SPI_CLC_RMC_MASK	0xFF
++#define LQ_SPI_CLC_DISS	BIT(1)	/* Disable status bit */
++#define LQ_SPI_CLC_DISR	BIT(0)	/* Disable request bit */
++
++#define LQ_SPI_ID_TXFS_SHIFT	24	/* Implemented TX FIFO size */
++#define LQ_SPI_ID_TXFS_MASK	0x3F
++#define LQ_SPI_ID_RXFS_SHIFT	16	/* Implemented RX FIFO size */
++#define LQ_SPI_ID_RXFS_MASK	0x3F
++#define LQ_SPI_ID_REV_MASK	0x1F	/* Hardware revision number */
++#define LQ_SPI_ID_CFG		BIT(5)	/* DMA interface support */
++
++#define LQ_SPI_CON_BM_SHIFT	16	/* Data width selection */
++#define LQ_SPI_CON_BM_MASK	0x1F
++#define LQ_SPI_CON_EM		BIT(24)	/* Echo mode */
++#define LQ_SPI_CON_IDLE	BIT(23)	/* Idle bit value */
++#define LQ_SPI_CON_ENBV	BIT(22)	/* Enable byte valid control */
++#define LQ_SPI_CON_RUEN	BIT(12)	/* Receive underflow error enable */
++#define LQ_SPI_CON_TUEN	BIT(11)	/* Transmit underflow error enable */
++#define LQ_SPI_CON_AEN		BIT(10)	/* Abort error enable */
++#define LQ_SPI_CON_REN		BIT(9)	/* Receive overflow error enable */
++#define LQ_SPI_CON_TEN		BIT(8)	/* Transmit overflow error enable */
++#define LQ_SPI_CON_LB		BIT(7)	/* Loopback control */
++#define LQ_SPI_CON_PO		BIT(6)	/* Clock polarity control */
++#define LQ_SPI_CON_PH		BIT(5)	/* Clock phase control */
++#define LQ_SPI_CON_HB		BIT(4)	/* Heading control */
++#define LQ_SPI_CON_RXOFF	BIT(1)	/* Switch receiver off */
++#define LQ_SPI_CON_TXOFF	BIT(0)	/* Switch transmitter off */
++
++#define LQ_SPI_STAT_RXBV_MASK	0x7
++#define LQ_SPI_STAT_RXBV_SHIFT	28
++#define LQ_SPI_STAT_BSY	BIT(13)	/* Busy flag */
++#define LQ_SPI_STAT_RUE	BIT(12)	/* Receive underflow error flag */
++#define LQ_SPI_STAT_TUE	BIT(11)	/* Transmit underflow error flag */
++#define LQ_SPI_STAT_AE		BIT(10)	/* Abort error flag */
++#define LQ_SPI_STAT_RE		BIT(9)	/* Receive error flag */
++#define LQ_SPI_STAT_TE		BIT(8)	/* Transmit error flag */
++#define LQ_SPI_STAT_MS		BIT(1)	/* Master/slave select bit */
++#define LQ_SPI_STAT_EN		BIT(0)	/* Enable bit */
++
++#define LQ_SPI_WHBSTATE_SETTUE	BIT(15)	/* Set transmit underflow error flag */
++#define LQ_SPI_WHBSTATE_SETAE	BIT(14)	/* Set abort error flag */
++#define LQ_SPI_WHBSTATE_SETRE	BIT(13)	/* Set receive error flag */
++#define LQ_SPI_WHBSTATE_SETTE	BIT(12)	/* Set transmit error flag */
++#define LQ_SPI_WHBSTATE_CLRTUE	BIT(11)	/* Clear transmit underflow error flag */
++#define LQ_SPI_WHBSTATE_CLRAE	BIT(10)	/* Clear abort error flag */
++#define LQ_SPI_WHBSTATE_CLRRE	BIT(9)	/* Clear receive error flag */
++#define LQ_SPI_WHBSTATE_CLRTE	BIT(8)	/* Clear transmit error flag */
++#define LQ_SPI_WHBSTATE_SETME	BIT(7)	/* Set mode error flag */
++#define LQ_SPI_WHBSTATE_CLRME	BIT(6)	/* Clear mode error flag */
++#define LQ_SPI_WHBSTATE_SETRUE	BIT(5)	/* Set receive underflow error flag */
++#define LQ_SPI_WHBSTATE_CLRRUE	BIT(4)	/* Clear receive underflow error flag */
++#define LQ_SPI_WHBSTATE_SETMS	BIT(3)	/* Set master select bit */
++#define LQ_SPI_WHBSTATE_CLRMS	BIT(2)	/* Clear master select bit */
++#define LQ_SPI_WHBSTATE_SETEN	BIT(1)	/* Set enable bit (operational mode) */
++#define LQ_SPI_WHBSTATE_CLREN	BIT(0)	/* Clear enable bit (config mode */
++#define LQ_SPI_WHBSTATE_CLR_ERRORS	0x0F50
++
++#define LQ_SPI_RXFCON_RXFITL_SHIFT	8	/* FIFO interrupt trigger level */
++#define LQ_SPI_RXFCON_RXFITL_MASK	0x3F
++#define LQ_SPI_RXFCON_RXFLU		BIT(1)	/* FIFO flush */
++#define LQ_SPI_RXFCON_RXFEN		BIT(0)	/* FIFO enable */
++
++#define LQ_SPI_TXFCON_TXFITL_SHIFT	8	/* FIFO interrupt trigger level */
++#define LQ_SPI_TXFCON_TXFITL_MASK	0x3F
++#define LQ_SPI_TXFCON_TXFLU		BIT(1)	/* FIFO flush */
++#define LQ_SPI_TXFCON_TXFEN		BIT(0)	/* FIFO enable */
++
++#define LQ_SPI_FSTAT_RXFFL_MASK	0x3f
++#define LQ_SPI_FSTAT_RXFFL_SHIFT	0
++#define LQ_SPI_FSTAT_TXFFL_MASK	0x3f
++#define LQ_SPI_FSTAT_TXFFL_SHIFT	8
++
++#define LQ_SPI_GPOCON_ISCSBN_SHIFT	8
++#define LQ_SPI_GPOCON_INVOUTN_SHIFT	0
++
++#define LQ_SPI_FGPO_SETOUTN_SHIFT	8
++#define LQ_SPI_FGPO_CLROUTN_SHIFT	0
++
++#define LQ_SPI_RXREQ_RXCNT_MASK	0xFFFF	/* Receive count value */
++#define LQ_SPI_RXCNT_TODO_MASK		0xFFFF	/* Recevie to-do value */
++
++#define LQ_SPI_IRNEN_F		BIT(3)	/* Frame end interrupt request */
++#define LQ_SPI_IRNEN_E		BIT(2)	/* Error end interrupt request */
++#define LQ_SPI_IRNEN_T		BIT(1)	/* Transmit end interrupt request */
++#define LQ_SPI_IRNEN_R		BIT(0)	/* Receive end interrupt request */
++#define LQ_SPI_IRNEN_ALL	0xF
++
++/* Hard-wired GPIOs used by SPI controller */
++#define LQ_SPI_GPIO_DI 	16
++#define LQ_SPI_GPIO_DO		17
++#define LQ_SPI_GPIO_CLK	18
++
++struct lq_spi {
++	struct spi_bitbang	bitbang;
++	struct completion	done;
++	spinlock_t		lock;
++
++	struct device		*dev;
++	void __iomem		*base;
++	struct clk		*clk;
++
++	int			status;
++	int			irq[3];
++
++	const u8		*tx;
++	u8			*rx;
++	u32			tx_cnt;
++	u32			rx_cnt;
++	u32			len;
++	struct spi_transfer	*curr_transfer;
++
++	u32 (*get_tx) (struct lq_spi *);
++
++	u16			txfs;
++	u16			rxfs;
++	unsigned		dma_support:1;
++	unsigned		cfg_mode:1;
++
++};
++
++struct lq_spi_controller_state {
++	void (*cs_activate) (struct spi_device *);
++	void (*cs_deactivate) (struct spi_device *);
++};
++
++struct lq_spi_irq_map {
++	char		*name;
++	irq_handler_t	handler;
++};
++
++struct lq_spi_cs_gpio_map {
++	unsigned	gpio;
++	unsigned	altsel0;
++	unsigned	altsel1;
++};
++
++static inline struct lq_spi *lq_spi_to_hw(struct spi_device *spi)
++{
++	return spi_master_get_devdata(spi->master);
++}
++
++static inline u32 lq_spi_reg_read(struct lq_spi *hw, u32 reg)
++{
++	return ioread32be(hw->base + reg);
++}
++
++static inline void lq_spi_reg_write(struct lq_spi *hw, u32 val, u32 reg)
++{
++	iowrite32be(val, hw->base + reg);
++}
++
++static inline void lq_spi_reg_setbit(struct lq_spi *hw, u32 bits, u32 reg)
++{
++	u32 val;
++
++	val = lq_spi_reg_read(hw, reg);
++	val |= bits;
++	lq_spi_reg_write(hw, val, reg);
++}
++
++static inline void lq_spi_reg_clearbit(struct lq_spi *hw, u32 bits, u32 reg)
++{
++	u32 val;
++
++	val = lq_spi_reg_read(hw, reg);
++	val &= ~bits;
++	lq_spi_reg_write(hw, val, reg);
++}
++
++static void lq_spi_hw_enable(struct lq_spi *hw)
++{
++	u32 clc;
++
++	/* Power-up mdule */
++	lq_pmu_enable(PMU_SPI);
++
++	/*
++	 * Set clock divider for run mode to 1 to
++	 * run at same frequency as FPI bus
++	 */
++	clc = (1 << LQ_SPI_CLC_RMC_SHIFT);
++	lq_spi_reg_write(hw, clc, LQ_SPI_CLC);
++}
++
++static void lq_spi_hw_disable(struct lq_spi *hw)
++{
++	/* Set clock divider to 0 and set module disable bit */
++	lq_spi_reg_write(hw, LQ_SPI_CLC_DISS, LQ_SPI_CLC);
++
++	/* Power-down mdule */
++	lq_pmu_disable(PMU_SPI);
++}
++
++static void lq_spi_reset_fifos(struct lq_spi *hw)
++{
++	u32 val;
++
++	/*
++	 * Enable and flush FIFOs. Set interrupt trigger level to
++	 * half of FIFO count implemented in hardware.
++	 */
++	if (hw->txfs > 1) {
++		val = hw->txfs << (LQ_SPI_TXFCON_TXFITL_SHIFT - 1);
++		val |= LQ_SPI_TXFCON_TXFEN | LQ_SPI_TXFCON_TXFLU;
++		lq_spi_reg_write(hw, val, LQ_SPI_TXFCON);
++	}
++
++	if (hw->rxfs > 1) {
++		val = hw->rxfs << (LQ_SPI_RXFCON_RXFITL_SHIFT - 1);
++		val |= LQ_SPI_RXFCON_RXFEN | LQ_SPI_RXFCON_RXFLU;
++		lq_spi_reg_write(hw, val, LQ_SPI_RXFCON);
++	}
++}
++
++static inline int lq_spi_wait_ready(struct lq_spi *hw)
++{
++	u32 stat;
++	unsigned long timeout;
++
++	timeout = jiffies + msecs_to_jiffies(200);
++
++	do {
++		stat = lq_spi_reg_read(hw, LQ_SPI_STAT);
++		if (!(stat & LQ_SPI_STAT_BSY))
++			return 0;
++
++		cond_resched();
++	} while (!time_after_eq(jiffies, timeout));
++
++	dev_err(hw->dev, "SPI wait ready timed out\n");
++
++	return -ETIMEDOUT;
++}
++
++static void lq_spi_config_mode_set(struct lq_spi *hw)
++{
++	if (hw->cfg_mode)
++		return;
++
++	/*
++	 * Putting the SPI module in config mode is only safe if no
++	 * transfer is in progress as indicated by busy flag STATE.BSY.
++	 */
++	if (lq_spi_wait_ready(hw)) {
++		lq_spi_reset_fifos(hw);
++		hw->status = -ETIMEDOUT;
++	}
++	lq_spi_reg_write(hw, LQ_SPI_WHBSTATE_CLREN, LQ_SPI_WHBSTATE);
++
++	hw->cfg_mode = 1;
++}
++
++static void lq_spi_run_mode_set(struct lq_spi *hw)
++{
++	if (!hw->cfg_mode)
++		return;
++
++	lq_spi_reg_write(hw, LQ_SPI_WHBSTATE_SETEN, LQ_SPI_WHBSTATE);
++
++	hw->cfg_mode = 0;
++}
++
++static u32 lq_spi_tx_word_u8(struct lq_spi *hw)
++{
++	const u8 *tx = hw->tx;
++	u32 data = *tx++;
++
++	hw->tx_cnt++;
++	hw->tx++;
++
++	return data;
++}
++
++static u32 lq_spi_tx_word_u16(struct lq_spi *hw)
++{
++	const u16 *tx = (u16 *) hw->tx;
++	u32 data = *tx++;
++
++	hw->tx_cnt += 2;
++	hw->tx += 2;
++
++	return data;
++}
++
++static u32 lq_spi_tx_word_u32(struct lq_spi *hw)
++{
++	const u32 *tx = (u32 *) hw->tx;
++	u32 data = *tx++;
++
++	hw->tx_cnt += 4;
++	hw->tx += 4;
++
++	return data;
++}
++
++static void lq_spi_bits_per_word_set(struct spi_device *spi)
++{
++	struct lq_spi *hw = lq_spi_to_hw(spi);
++	u32 bm;
++	u8 bits_per_word = spi->bits_per_word;
++
++	/*
++	 * Use either default value of SPI device or value
++	 * from current transfer.
++	 */
++	if (hw->curr_transfer && hw->curr_transfer->bits_per_word)
++		bits_per_word = hw->curr_transfer->bits_per_word;
++
++	if (bits_per_word <= 8)
++		hw->get_tx = lq_spi_tx_word_u8;
++	else if (bits_per_word <= 16)
++		hw->get_tx = lq_spi_tx_word_u16;
++	else if (bits_per_word <= 32)
++		hw->get_tx = lq_spi_tx_word_u32;
++
++	/* CON.BM value = bits_per_word - 1 */
++	bm = (bits_per_word - 1) << LQ_SPI_CON_BM_SHIFT;
++
++	lq_spi_reg_clearbit(hw, LQ_SPI_CON_BM_MASK <<
++			     LQ_SPI_CON_BM_SHIFT, LQ_SPI_CON);
++	lq_spi_reg_setbit(hw, bm, LQ_SPI_CON);
++}
++
++static void lq_spi_speed_set(struct spi_device *spi)
++{
++	struct lq_spi *hw = lq_spi_to_hw(spi);
++	u32 br, max_speed_hz, spi_clk;
++	u32 speed_hz = spi->max_speed_hz;
++
++	/*
++	 * Use either default value of SPI device or value
++	 * from current transfer.
++	 */
++	if (hw->curr_transfer && hw->curr_transfer->speed_hz)
++		speed_hz = hw->curr_transfer->speed_hz;
++
++	/*
++	 * SPI module clock is derived from FPI bus clock dependent on
++	 * divider value in CLC.RMS which is always set to 1.
++	 */
++	spi_clk = clk_get_rate(hw->clk);
++
++	/*
++	 * Maximum SPI clock frequency in master mode is half of
++	 * SPI module clock frequency. Maximum reload value of
++	 * baudrate generator BR is 2^16.
++	 */
++	max_speed_hz = spi_clk / 2;
++	if (speed_hz >= max_speed_hz)
++		br = 0;
++	else
++		br = (max_speed_hz / speed_hz) - 1;
++
++	if (br > 0xFFFF)
++		br = 0xFFFF;
++
++	lq_spi_reg_write(hw, br, LQ_SPI_BRT);
++}
++
++static void lq_spi_clockmode_set(struct spi_device *spi)
++{
++	struct lq_spi *hw = lq_spi_to_hw(spi);
++	u32 con;
++
++	con = lq_spi_reg_read(hw, LQ_SPI_CON);
++
++	/*
++	 * SPI mode mapping in CON register:
++	 * Mode CPOL CPHA CON.PO CON.PH
++	 *  0    0    0      0      1
++	 *  1    0    1      0      0
++	 *  2    1    0      1      1
++	 *  3    1    1      1      0
++	 */
++	if (spi->mode & SPI_CPHA)
++		con &= ~LQ_SPI_CON_PH;
++	else
++		con |= LQ_SPI_CON_PH;
++
++	if (spi->mode & SPI_CPOL)
++		con |= LQ_SPI_CON_PO;
++	else
++		con &= ~LQ_SPI_CON_PO;
++
++	/* Set heading control */
++	if (spi->mode & SPI_LSB_FIRST)
++		con &= ~LQ_SPI_CON_HB;
++	else
++		con |= LQ_SPI_CON_HB;
++
++	lq_spi_reg_write(hw, con, LQ_SPI_CON);
++}
++
++static void lq_spi_xmit_set(struct lq_spi *hw, struct spi_transfer *t)
++{
++	u32 con;
++
++	con = lq_spi_reg_read(hw, LQ_SPI_CON);
++
++	if (t) {
++		if (t->tx_buf && t->rx_buf) {
++			con &= ~(LQ_SPI_CON_TXOFF | LQ_SPI_CON_RXOFF);
++		} else if (t->rx_buf) {
++			con &= ~LQ_SPI_CON_RXOFF;
++			con |= LQ_SPI_CON_TXOFF;
++		} else if (t->tx_buf) {
++			con &= ~LQ_SPI_CON_TXOFF;
++			con |= LQ_SPI_CON_RXOFF;
++		}
++	} else
++		con |= (LQ_SPI_CON_TXOFF | LQ_SPI_CON_RXOFF);
++
++	lq_spi_reg_write(hw, con, LQ_SPI_CON);
++}
++
++static void lq_spi_gpio_cs_activate(struct spi_device *spi)
++{
++	struct lq_spi_controller_data *cdata = spi->controller_data;
++	int val = spi->mode & SPI_CS_HIGH ? 1 : 0;
++
++	gpio_set_value(cdata->gpio, val);
++}
++
++static void lq_spi_gpio_cs_deactivate(struct spi_device *spi)
++{
++	struct lq_spi_controller_data *cdata = spi->controller_data;
++	int val = spi->mode & SPI_CS_HIGH ? 0 : 1;
++
++	gpio_set_value(cdata->gpio, val);
++}
++
++static void lq_spi_internal_cs_activate(struct spi_device *spi)
++{
++	struct lq_spi *hw = lq_spi_to_hw(spi);
++	u32 fgpo;
++
++	fgpo = (1 << (spi->chip_select + LQ_SPI_FGPO_CLROUTN_SHIFT));
++	lq_spi_reg_setbit(hw, fgpo, LQ_SPI_FGPO);
++}
++
++static void lq_spi_internal_cs_deactivate(struct spi_device *spi)
++{
++	struct lq_spi *hw = lq_spi_to_hw(spi);
++	u32 fgpo;
++
++	fgpo = (1 << (spi->chip_select + LQ_SPI_FGPO_SETOUTN_SHIFT));
++	lq_spi_reg_setbit(hw, fgpo, LQ_SPI_FGPO);
++}
++
++static void lq_spi_chipselect(struct spi_device *spi, int cs)
++{
++	struct lq_spi *hw = lq_spi_to_hw(spi);
++	struct lq_spi_controller_state *cstate = spi->controller_state;
++
++	switch (cs) {
++	case BITBANG_CS_ACTIVE:
++		lq_spi_bits_per_word_set(spi);
++		lq_spi_speed_set(spi);
++		lq_spi_clockmode_set(spi);
++		lq_spi_run_mode_set(hw);
++
++		cstate->cs_activate(spi);
++		break;
++
++	case BITBANG_CS_INACTIVE:
++		cstate->cs_deactivate(spi);
++
++		lq_spi_config_mode_set(hw);
++
++		break;
++	}
++}
++
++static int lq_spi_setup_transfer(struct spi_device *spi,
++				  struct spi_transfer *t)
++{
++	struct lq_spi *hw = lq_spi_to_hw(spi);
++	u8 bits_per_word = spi->bits_per_word;
++
++	hw->curr_transfer = t;
++
++	if (t && t->bits_per_word)
++		bits_per_word = t->bits_per_word;
++
++	if (bits_per_word > 32)
++		return -EINVAL;
++
++	lq_spi_config_mode_set(hw);
++
++	return 0;
++}
++
++static const struct lq_spi_cs_gpio_map lq_spi_cs[] = {
++	{ 15, 1, 0 },
++	{ 22, 1, 0 },
++	{ 13, 0, 1 },
++	{ 10, 0, 1 },
++	{  9, 0, 1 },
++	{ 11, 1, 1 },
++};
++
++static int lq_spi_setup(struct spi_device *spi)
++{
++	struct lq_spi *hw = lq_spi_to_hw(spi);
++	struct lq_spi_controller_data *cdata = spi->controller_data;
++	struct lq_spi_controller_state *cstate;
++	u32 gpocon, fgpo;
++	int ret;
++
++	/* Set default word length to 8 if not set */
++	if (!spi->bits_per_word)
++		spi->bits_per_word = 8;
++
++	if (spi->bits_per_word > 32)
++		return -EINVAL;
++
++	if (!spi->controller_state) {
++		cstate = kzalloc(sizeof(struct lq_spi_controller_state),
++				 GFP_KERNEL);
++		if (!cstate)
++			return -ENOMEM;
++
++		spi->controller_state = cstate;
++	} else
++		return 0;
++
++	/*
++	 * Up to six GPIOs can be connected to the SPI module
++	 * via GPIO alternate function to control the chip select lines.
++	 * For more flexibility in board layout this driver can also control
++	 * the CS lines via GPIO API. If GPIOs should be used, board setup code
++	 * have to register the SPI device with struct lq_spi_controller_data
++	 * attached.
++	 */
++	if (cdata && cdata->gpio) {
++		ret = gpio_request(cdata->gpio, "spi-cs");
++		if (ret)
++			return -EBUSY;
++
++		ret = spi->mode & SPI_CS_HIGH ? 0 : 1;
++		gpio_direction_output(cdata->gpio, ret);
++
++		cstate->cs_activate = lq_spi_gpio_cs_activate;
++		cstate->cs_deactivate = lq_spi_gpio_cs_deactivate;
++	} else {
++		ret = lq_gpio_request(lq_spi_cs[spi->chip_select].gpio,
++				lq_spi_cs[spi->chip_select].altsel0,
++				lq_spi_cs[spi->chip_select].altsel1,
++				1, "spi-cs");
++		if (ret)
++			return -EBUSY;
++
++		gpocon = (1 << (spi->chip_select +
++				LQ_SPI_GPOCON_ISCSBN_SHIFT));
++
++		if (spi->mode & SPI_CS_HIGH)
++			gpocon |= (1 << spi->chip_select);
++
++		fgpo = (1 << (spi->chip_select + LQ_SPI_FGPO_SETOUTN_SHIFT));
++
++		lq_spi_reg_setbit(hw, gpocon, LQ_SPI_GPOCON);
++		lq_spi_reg_setbit(hw, fgpo, LQ_SPI_FGPO);
++
++		cstate->cs_activate = lq_spi_internal_cs_activate;
++		cstate->cs_deactivate = lq_spi_internal_cs_deactivate;
++	}
++
++	return 0;
++}
++
++static void lq_spi_cleanup(struct spi_device *spi)
++{
++	struct lq_spi_controller_data *cdata = spi->controller_data;
++	struct lq_spi_controller_state *cstate = spi->controller_state;
++	unsigned gpio;
++
++	if (cdata && cdata->gpio)
++		gpio = cdata->gpio;
++	else
++		gpio = lq_spi_cs[spi->chip_select].gpio;
++
++	gpio_free(gpio);
++	kfree(cstate);
++}
++
++static void lq_spi_txfifo_write(struct lq_spi *hw)
++{
++	u32 fstat, data;
++	u16 fifo_space;
++
++	/* Determine how much FIFOs are free for TX data */
++	fstat = lq_spi_reg_read(hw, LQ_SPI_FSTAT);
++	fifo_space = hw->txfs - ((fstat >> LQ_SPI_FSTAT_TXFFL_SHIFT) &
++					LQ_SPI_FSTAT_TXFFL_MASK);
++
++	if (!fifo_space)
++		return;
++
++	while (hw->tx_cnt < hw->len && fifo_space) {
++		data = hw->get_tx(hw);
++		lq_spi_reg_write(hw, data, LQ_SPI_TB);
++		fifo_space--;
++	}
++}
++
++static void lq_spi_rxfifo_read(struct lq_spi *hw)
++{
++	u32 fstat, data, *rx32;
++	u16 fifo_fill;
++	u8 rxbv, shift, *rx8;
++
++	/* Determine how much FIFOs are filled with RX data */
++	fstat = lq_spi_reg_read(hw, LQ_SPI_FSTAT);
++	fifo_fill = ((fstat >> LQ_SPI_FSTAT_RXFFL_SHIFT)
++			& LQ_SPI_FSTAT_RXFFL_MASK);
++
++	if (!fifo_fill)
++		return;
++
++	/*
++	 * The 32 bit FIFO is always used completely independent from the
++	 * bits_per_word value. Thus four bytes have to be read at once
++	 * per FIFO.
++	 */
++	rx32 = (u32 *) hw->rx;
++	while (hw->len - hw->rx_cnt >= 4 && fifo_fill) {
++		*rx32++ = lq_spi_reg_read(hw, LQ_SPI_RB);
++		hw->rx_cnt += 4;
++		hw->rx += 4;
++		fifo_fill--;
++	}
++
++	/*
++	 * If there are remaining bytes, read byte count from STAT.RXBV
++	 * register and read the data byte-wise.
++	 */
++	while (fifo_fill && hw->rx_cnt < hw->len) {
++		rxbv = (lq_spi_reg_read(hw, LQ_SPI_STAT) >>
++			LQ_SPI_STAT_RXBV_SHIFT) & LQ_SPI_STAT_RXBV_MASK;
++		data = lq_spi_reg_read(hw, LQ_SPI_RB);
++
++		shift = (rxbv - 1) * 8;
++		rx8 = hw->rx;
++
++		while (rxbv) {
++			*rx8++ = (data >> shift) & 0xFF;
++			rxbv--;
++			shift -= 8;
++			hw->rx_cnt++;
++			hw->rx++;
++		}
++
++		fifo_fill--;
++	}
++}
++
++static void lq_spi_rxreq_set(struct lq_spi *hw)
++{
++	u32 rxreq, rxreq_max, rxtodo;
++
++	rxtodo = lq_spi_reg_read(hw, LQ_SPI_RXCNT) & LQ_SPI_RXCNT_TODO_MASK;
++
++	/*
++	 * In RX-only mode the serial clock is activated only after writing
++	 * the expected amount of RX bytes into RXREQ register.
++	 * To avoid receive overflows at high clocks it is better to request
++	 * only the amount of bytes that fits into all FIFOs. This value
++	 * depends on the FIFO size implemented in hardware.
++	 */
++	rxreq = hw->len - hw->rx_cnt;
++	rxreq_max = hw->rxfs << 2;
++	rxreq = min(rxreq_max, rxreq);
++
++	if (!rxtodo && rxreq)
++		lq_spi_reg_write(hw, rxreq, LQ_SPI_RXREQ);
++}
++
++static inline void lq_spi_complete(struct lq_spi *hw)
++{
++	complete(&hw->done);
++}
++
++irqreturn_t lq_spi_tx_irq(int irq, void *data)
++{
++	struct lq_spi *hw = data;
++	unsigned long flags;
++	int completed = 0;
++
++	spin_lock_irqsave(&hw->lock, flags);
++
++	if (hw->tx_cnt < hw->len)
++		lq_spi_txfifo_write(hw);
++
++	if (hw->tx_cnt == hw->len)
++		completed = 1;
++
++	spin_unlock_irqrestore(&hw->lock, flags);
++
++	if (completed)
++		lq_spi_complete(hw);
++
++	return IRQ_HANDLED;
++}
++
++irqreturn_t lq_spi_rx_irq(int irq, void *data)
++{
++	struct lq_spi *hw = data;
++	unsigned long flags;
++	int completed = 0;
++
++	spin_lock_irqsave(&hw->lock, flags);
++
++	if (hw->rx_cnt < hw->len) {
++		lq_spi_rxfifo_read(hw);
++
++		if (hw->tx && hw->tx_cnt < hw->len)
++			lq_spi_txfifo_write(hw);
++	}
++
++	if (hw->rx_cnt == hw->len)
++		completed = 1;
++	else if (!hw->tx)
++		lq_spi_rxreq_set(hw);
++
++	spin_unlock_irqrestore(&hw->lock, flags);
++
++	if (completed)
++		lq_spi_complete(hw);
++
++	return IRQ_HANDLED;
++}
++
++irqreturn_t lq_spi_err_irq(int irq, void *data)
++{
++	struct lq_spi *hw = data;
++	unsigned long flags;
++
++	spin_lock_irqsave(&hw->lock, flags);
++
++	/* Disable all interrupts */
++	lq_spi_reg_clearbit(hw, LQ_SPI_IRNEN_ALL, LQ_SPI_IRNEN);
++
++	/* Clear all error flags */
++	lq_spi_reg_write(hw, LQ_SPI_WHBSTATE_CLR_ERRORS, LQ_SPI_WHBSTATE);
++
++	/* Flush FIFOs */
++	lq_spi_reg_setbit(hw, LQ_SPI_RXFCON_RXFLU, LQ_SPI_RXFCON);
++	lq_spi_reg_setbit(hw, LQ_SPI_TXFCON_TXFLU, LQ_SPI_TXFCON);
++
++	hw->status = -EIO;
++	spin_unlock_irqrestore(&hw->lock, flags);
++
++	lq_spi_complete(hw);
++
++	return IRQ_HANDLED;
++}
++
++static int lq_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
++{
++	struct lq_spi *hw = lq_spi_to_hw(spi);
++	u32 irq_flags = 0;
++
++	hw->tx = t->tx_buf;
++	hw->rx = t->rx_buf;
++	hw->len = t->len;
++	hw->tx_cnt = 0;
++	hw->rx_cnt = 0;
++	hw->status = 0;
++	INIT_COMPLETION(hw->done);
++
++	lq_spi_xmit_set(hw, t);
++
++	/* Enable error interrupts */
++	lq_spi_reg_setbit(hw, LQ_SPI_IRNEN_E, LQ_SPI_IRNEN);
++
++	if (hw->tx) {
++		/* Initially fill TX FIFO with as much data as possible */
++		lq_spi_txfifo_write(hw);
++		irq_flags |= LQ_SPI_IRNEN_T;
++
++		/* Always enable RX interrupt in Full Duplex mode */
++		if (hw->rx)
++			irq_flags |= LQ_SPI_IRNEN_R;
++	} else if (hw->rx) {
++		/* Start RX clock */
++		lq_spi_rxreq_set(hw);
++
++		/* Enable RX interrupt to receive data from RX FIFOs */
++		irq_flags |= LQ_SPI_IRNEN_R;
++	}
++
++	/* Enable TX or RX interrupts */
++	lq_spi_reg_setbit(hw, irq_flags, LQ_SPI_IRNEN);
++	wait_for_completion_interruptible(&hw->done);
++
++	/* Disable all interrupts */
++	lq_spi_reg_clearbit(hw, LQ_SPI_IRNEN_ALL, LQ_SPI_IRNEN);
++
++	/*
++	 * Return length of current transfer for bitbang utility code if
++	 * no errors occured during transmission.
++	 */
++	if (!hw->status)
++		hw->status = hw->len;
++
++	return hw->status;
++}
++
++static const struct lq_spi_irq_map lq_spi_irqs[] = {
++	{ "spi_tx", lq_spi_tx_irq },
++	{ "spi_rx", lq_spi_rx_irq },
++	{ "spi_err", lq_spi_err_irq },
++};
++
++static int __init lq_spi_probe(struct platform_device *pdev)
++{
++	struct spi_master *master;
++	struct resource *r;
++	struct lq_spi *hw;
++	struct lq_spi_platform_data *pdata = pdev->dev.platform_data;
++	int ret, i;
++	u32 data, id;
++
++	master = spi_alloc_master(&pdev->dev, sizeof(struct lq_spi));
++	if (!master) {
++		dev_err(&pdev->dev, "spi_alloc_master\n");
++		ret = -ENOMEM;
++		goto err;
++	}
++
++	hw = spi_master_get_devdata(master);
++
++	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (r == NULL) {
++		dev_err(&pdev->dev, "platform_get_resource\n");
++		ret = -ENOENT;
++		goto err_master;
++	}
++
++	r = devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
++			pdev->name);
++	if (!r) {
++		dev_err(&pdev->dev, "devm_request_mem_region\n");
++		ret = -ENXIO;
++		goto err_master;
++	}
++
++	hw->base = devm_ioremap_nocache(&pdev->dev, r->start, resource_size(r));
++	if (!hw->base) {
++		dev_err(&pdev->dev, "devm_ioremap_nocache\n");
++		ret = -ENXIO;
++		goto err_master;
++	}
++
++	hw->clk = clk_get(&pdev->dev, "fpi");
++	if (IS_ERR(hw->clk)) {
++		dev_err(&pdev->dev, "clk_get\n");
++		ret = PTR_ERR(hw->clk);
++		goto err_master;
++	}
++
++	memset(hw->irq, 0, sizeof(hw->irq));
++	for (i = 0; i < ARRAY_SIZE(lq_spi_irqs); i++) {
++		ret = platform_get_irq_byname(pdev, lq_spi_irqs[i].name);
++		if (0 > ret) {
++			dev_err(&pdev->dev, "platform_get_irq_byname\n");
++			goto err_irq;
++		}
++
++		hw->irq[i] = ret;
++		ret = request_irq(hw->irq[i], lq_spi_irqs[i].handler,
++				  0, lq_spi_irqs[i].name, hw);
++		if (ret) {
++			dev_err(&pdev->dev, "request_irq\n");
++			goto err_irq;
++		}
++	}
++
++	hw->bitbang.master = spi_master_get(master);
++	hw->bitbang.chipselect = lq_spi_chipselect;
++	hw->bitbang.setup_transfer = lq_spi_setup_transfer;
++	hw->bitbang.txrx_bufs = lq_spi_txrx_bufs;
++
++	master->bus_num = pdev->id;
++	master->num_chipselect = pdata->num_chipselect;
++	master->setup = lq_spi_setup;
++	master->cleanup = lq_spi_cleanup;
++
++	hw->dev = &pdev->dev;
++	init_completion(&hw->done);
++	spin_lock_init(&hw->lock);
++
++	/* Set GPIO alternate functions to SPI */
++	lq_gpio_request(LQ_SPI_GPIO_DI, 1, 0, 0, "spi-di");
++	lq_gpio_request(LQ_SPI_GPIO_DO, 1, 0, 1, "spi-do");
++	lq_gpio_request(LQ_SPI_GPIO_CLK, 1, 0, 1, "spi-clk");
++
++	lq_spi_hw_enable(hw);
++
++	/* Read module capabilities */
++	id = lq_spi_reg_read(hw, LQ_SPI_ID);
++	hw->txfs = (id >> LQ_SPI_ID_TXFS_SHIFT) & LQ_SPI_ID_TXFS_MASK;
++	hw->rxfs = (id >> LQ_SPI_ID_TXFS_SHIFT) & LQ_SPI_ID_TXFS_MASK;
++	hw->dma_support = (id & LQ_SPI_ID_CFG) ? 1 : 0;
++
++	lq_spi_config_mode_set(hw);
++
++	/* Enable error checking, disable TX/RX, set idle value high */
++	data = LQ_SPI_CON_RUEN | LQ_SPI_CON_AEN |
++	    LQ_SPI_CON_TEN | LQ_SPI_CON_REN |
++	    LQ_SPI_CON_TXOFF | LQ_SPI_CON_RXOFF | LQ_SPI_CON_IDLE;
++	lq_spi_reg_write(hw, data, LQ_SPI_CON);
++
++	/* Enable master mode and clear error flags */
++	lq_spi_reg_write(hw, LQ_SPI_WHBSTATE_SETMS |
++			  LQ_SPI_WHBSTATE_CLR_ERRORS, LQ_SPI_WHBSTATE);
++
++	/* Reset GPIO/CS registers */
++	lq_spi_reg_write(hw, 0x0, LQ_SPI_GPOCON);
++	lq_spi_reg_write(hw, 0xFF00, LQ_SPI_FGPO);
++
++	/* Enable and flush FIFOs */
++	lq_spi_reset_fifos(hw);
++
++	ret = spi_bitbang_start(&hw->bitbang);
++	if (ret) {
++		dev_err(&pdev->dev, "spi_bitbang_start\n");
++		goto err_bitbang;
++	}
++
++	platform_set_drvdata(pdev, hw);
++
++	pr_info("Lantiq SoC SPI controller rev %u (TXFS %u, RXFS %u, DMA %u)\n",
++		id & LQ_SPI_ID_REV_MASK, hw->txfs, hw->rxfs, hw->dma_support);
++
++	return 0;
++
++err_bitbang:
++	lq_spi_hw_disable(hw);
++
++err_irq:
++	clk_put(hw->clk);
++
++	for (; i > 0; i--)
++		free_irq(hw->irq[i], hw);
++
++err_master:
++	spi_master_put(master);
++
++err:
++	return ret;
++}
++
++static int __exit lq_spi_remove(struct platform_device *pdev)
++{
++	struct lq_spi *hw = platform_get_drvdata(pdev);
++	int ret, i;
++
++	ret = spi_bitbang_stop(&hw->bitbang);
++	if (ret)
++		return ret;
++
++	platform_set_drvdata(pdev, NULL);
++
++	lq_spi_config_mode_set(hw);
++	lq_spi_hw_disable(hw);
++
++	for (i = 0; i < ARRAY_SIZE(hw->irq); i++)
++		if (0 < hw->irq[i])
++			free_irq(hw->irq[i], hw);
++
++	gpio_free(LQ_SPI_GPIO_DI);
++	gpio_free(LQ_SPI_GPIO_DO);
++	gpio_free(LQ_SPI_GPIO_CLK);
++
++	clk_put(hw->clk);
++	spi_master_put(hw->bitbang.master);
++
++	return 0;
++}
++
++static struct platform_driver lq_spi_driver = {
++	.driver = {
++		   .name = "ltq-spi",
++		   .owner = THIS_MODULE,
++		   },
++	.remove = __exit_p(lq_spi_remove),
++};
++
++static int __init lq_spi_init(void)
++{
++	return platform_driver_probe(&lq_spi_driver, lq_spi_probe);
++}
++module_init(lq_spi_init);
++
++static void __exit lq_spi_exit(void)
++{
++	platform_driver_unregister(&lq_spi_driver);
++}
++module_exit(lq_spi_exit);
++
++MODULE_DESCRIPTION("Lantiq SoC SPI controller driver");
++MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ltq-spi");
diff --git a/target/linux/lantiq/patches/942-spi3.patch b/target/linux/lantiq/patches/942-spi3.patch
new file mode 100644
index 0000000..c09125f
--- /dev/null
+++ b/target/linux/lantiq/patches/942-spi3.patch
@@ -0,0 +1,66 @@
+From: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
+Date: Thu, 3 Mar 2011 20:42:26 +0000 (+0100)
+Subject: MIPS: lantiq: Add device register helper for SPI controller and devices
+X-Git-Url: http://nbd.name/gitweb.cgi?p=lantiq.git;a=commitdiff_plain;h=b35b07062b718ece9b9cb7b23b12d83a087eafb0;hp=653c95b8b9066c9c6ac08bd64d0ceee439e9fd90
+
+MIPS: lantiq: Add device register helper for SPI controller and devices
+
+Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
+---
+
+--- a/arch/mips/lantiq/xway/devices.c
++++ b/arch/mips/lantiq/xway/devices.c
+@@ -22,6 +22,7 @@
+ #include <linux/gpio.h>
+ #include <linux/gpio_buttons.h>
+ #include <linux/leds.h>
++#include <linux/spi/spi.h>
+ 
+ #include <asm/bootinfo.h>
+ #include <asm/irq.h>
+@@ -332,5 +333,27 @@
+ 	lantiq_emulate_madwifi_eep = 1;
+ }
+ 
++static struct resource lq_spi_resources[] = {
++	{
++		.start  = LQ_SSC_BASE_ADDR,
++		.end    = LQ_SSC_BASE_ADDR + LQ_SSC_SIZE - 1,
++		.flags  = IORESOURCE_MEM,
++	},
++	IRQ_RES(spi_tx, LQ_SSC_TIR),
++	IRQ_RES(spi_rx, LQ_SSC_RIR),
++	IRQ_RES(spi_err, LQ_SSC_EIR),
++};
+ 
++static struct platform_device lq_spi = {
++	.name		= "ltq-spi",
++	.resource	= lq_spi_resources,
++	.num_resources	= ARRAY_SIZE(lq_spi_resources),
++};
+ 
++void __init lq_register_spi(struct lq_spi_platform_data *pdata,
++		struct spi_board_info const *info, unsigned n)
++{
++	spi_register_board_info(info, n);
++	lq_spi.dev.platform_data = pdata;
++	platform_device_register(&lq_spi);
++}
+--- a/arch/mips/lantiq/xway/devices.h
++++ b/arch/mips/lantiq/xway/devices.h
+@@ -11,6 +11,7 @@
+ 
+ #include <lantiq_platform.h>
+ #include <xway_irq.h>
++#include <linux/spi/spi.h>
+ 
+ extern void __init lq_register_gpio(void);
+ extern void __init lq_register_gpio_stp(void);
+@@ -25,5 +26,7 @@
+ extern void __init lq_register_asc(int port);
+ extern void __init lq_register_gpio_buttons(struct gpio_button *buttons, int cnt);
+ extern void __init lq_register_crypto(const char *name);
++extern void lq_register_spi(struct lq_spi_platform_data *pdata,
++		struct spi_board_info const *info, unsigned n);
+ 
+ #endif
diff --git a/target/linux/lantiq/xway/config-default b/target/linux/lantiq/xway/config-default
index bb4298d..bcd0521 100644
--- a/target/linux/lantiq/xway/config-default
+++ b/target/linux/lantiq/xway/config-default
@@ -19,4 +19,9 @@ CONFIG_LANTIQ_PROM_ASC1=y
 CONFIG_RTL8306_PHY=y
 # CONFIG_SOC_LANTIQ_FALCON is not set
 CONFIG_SOC_LANTIQ_XWAY=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_LANTIQ=y
+CONFIG_SPI_MASTER=y
 CONFIG_USB_SUPPORT=y