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authorFlorian Fainelli <florian@openwrt.org>2012-06-19 14:48:56 +0000
committerFlorian Fainelli <florian@openwrt.org>2012-06-19 14:48:56 +0000
commitf4afa00862b7db8a2da8c012843a286716c0a534 (patch)
tree9c15efab8fd398654de98648e07f26c51d6eec66 /target/linux/mcs814x/files-3.3/arch/arm/mach-mcs814x/common.c
parent7c87391c55a713a9ef9df169ab23e79177184b1a (diff)
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add Moschip MSC814x support
This target currently only supports Moschip's MCS8140 SoC, but support for other chips in the same family (MCS8142, MCS8144) will be easy to add. Target support is entirely using Device Tree for probing peripherals. Drivers support include: - PCI - USB 1 & 2 - watchdog - random number generator - UART - timer - internal Ethernet PHY - Ethernet MAC core Support for the following boards is included using Device Tree - Devolo dLAN USB Extender - Tigal RBT-832 SVN-Revision: 32462
Diffstat (limited to 'target/linux/mcs814x/files-3.3/arch/arm/mach-mcs814x/common.c')
-rw-r--r--target/linux/mcs814x/files-3.3/arch/arm/mach-mcs814x/common.c92
1 files changed, 92 insertions, 0 deletions
diff --git a/target/linux/mcs814x/files-3.3/arch/arm/mach-mcs814x/common.c b/target/linux/mcs814x/files-3.3/arch/arm/mach-mcs814x/common.c
new file mode 100644
index 0000000..a408e69
--- /dev/null
+++ b/target/linux/mcs814x/files-3.3/arch/arm/mach-mcs814x/common.c
@@ -0,0 +1,92 @@
+/*
+ * arch/arm/mach-mcs814x/common.c
+ *
+ * Core functions for Moschip MCS814x SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/hardware.h>
+#include <mach/cpu.h>
+#include <asm/pgtable.h>
+#include <asm/mach/map.h>
+
+static struct map_desc mcs814x_io_desc[] __initdata = {
+ {
+ .virtual = MCS814X_IO_BASE,
+ .pfn = __phys_to_pfn(MCS814X_IO_START),
+ .length = MCS814X_IO_SIZE,
+ .type = MT_DEVICE
+ },
+};
+
+#define SYSDBG_BS2 0x04
+#define CPU_MODE_SHIFT 23
+#define CPU_MODE_MASK 0x03
+
+struct cpu_mode {
+ const char *name;
+ int gpio_start;
+ int gpio_end;
+};
+
+static const struct cpu_mode cpu_modes[] = {
+ {
+ .name = "I2S",
+ .gpio_start = 4,
+ .gpio_end = 8,
+ },
+ {
+ .name = "UART",
+ .gpio_start = 4,
+ .gpio_end = 9,
+ },
+ {
+ .name = "External MII",
+ .gpio_start = 0,
+ .gpio_end = 16,
+ },
+ {
+ .name = "Normal",
+ .gpio_start = -1,
+ .gpio_end = -1,
+ },
+};
+
+void __init mcs814x_init_machine(void)
+{
+ u32 bs2, cpu_mode;
+ int gpio;
+
+ bs2 = __raw_readl(_CONFADDR_SYSDBG + SYSDBG_BS2);
+ cpu_mode = (bs2 >> CPU_MODE_SHIFT) & CPU_MODE_MASK;
+
+ pr_info("CPU mode: %s\n", cpu_modes[cpu_mode].name);
+
+ /* request the gpios since the pins are muxed for functionnality */
+ for (gpio = cpu_modes[cpu_mode].gpio_start;
+ gpio == cpu_modes[cpu_mode].gpio_end; gpio++) {
+ if (gpio != -1)
+ gpio_request(gpio, cpu_modes[cpu_mode].name);
+ }
+}
+
+void __init mcs814x_map_io(void)
+{
+ iotable_init(mcs814x_io_desc, ARRAY_SIZE(mcs814x_io_desc));
+}
+
+void mcs814x_restart(char mode, const char *cmd)
+{
+ __raw_writel(~(1 << 31), _CONFADDR_SYSDBG);
+}