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author | John Crispin <john@openwrt.org> | 2016-03-21 20:42:51 +0000 |
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committer | John Crispin <john@openwrt.org> | 2016-03-21 20:42:51 +0000 |
commit | 5d2f529c9b83d5f769258928b5ddd82f4dc9979e (patch) | |
tree | 65ecb999d7bfda861006ffba75f375c1d7c8260d /target/linux/mediatek/patches/0044-dt-bindings-Add-usb3.0-phy-binding-for-MT65xx-SoCs.patch | |
parent | c8a6c583fc5f5c0834f993b591d6bb52d958c99a (diff) | |
download | mtk-20170518-5d2f529c9b83d5f769258928b5ddd82f4dc9979e.zip mtk-20170518-5d2f529c9b83d5f769258928b5ddd82f4dc9979e.tar.gz mtk-20170518-5d2f529c9b83d5f769258928b5ddd82f4dc9979e.tar.bz2 |
mediatek: bump to v4.4
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 49064
Diffstat (limited to 'target/linux/mediatek/patches/0044-dt-bindings-Add-usb3.0-phy-binding-for-MT65xx-SoCs.patch')
-rw-r--r-- | target/linux/mediatek/patches/0044-dt-bindings-Add-usb3.0-phy-binding-for-MT65xx-SoCs.patch | 54 |
1 files changed, 0 insertions, 54 deletions
diff --git a/target/linux/mediatek/patches/0044-dt-bindings-Add-usb3.0-phy-binding-for-MT65xx-SoCs.patch b/target/linux/mediatek/patches/0044-dt-bindings-Add-usb3.0-phy-binding-for-MT65xx-SoCs.patch deleted file mode 100644 index 4b3fc67..0000000 --- a/target/linux/mediatek/patches/0044-dt-bindings-Add-usb3.0-phy-binding-for-MT65xx-SoCs.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 8d61eb953496aba51b94dac07c31c7e069c784bd Mon Sep 17 00:00:00 2001 -From: Chunfeng Yun <chunfeng.yun@mediatek.com> -Date: Wed, 27 May 2015 19:47:58 +0800 -Subject: [PATCH 44/76] dt-bindings: Add usb3.0 phy binding for MT65xx SoCs - -add a DT binding documentation of usb3.0 phy for MT65xx -SoCs from Mediatek. - -Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> ---- - .../devicetree/bindings/usb/mt65xx-u3phy.txt | 37 ++++++++++++++++++++ - 1 file changed, 37 insertions(+) - create mode 100644 Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt - ---- /dev/null -+++ b/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt -@@ -0,0 +1,37 @@ -+MT65xx U3PHY -+ -+The device node for Mediatek SOC usb3.0 phy -+ -+Required properties: -+ - compatible : Should be "mediatek,mt8173-u3phy" -+ - reg : Offset and length of registers, the first is for mac domain, -+ another for phy domain -+ - power-domains: to enable usb's mtcmos -+ - reg-vusb33-supply: regulator of usb avdd3.3v -+ - clocks : must support all clocks that phy need -+ - clock-names: should be "wakeup_deb_p0", "wakeup_deb_p1" for wakeup -+ debounce control clocks, "sys_mac" for sys and mac clocks and -+ "u3phya_ref" for u3phya reference clock. -+ -+Optional properties: -+ - disable-usb2-p1 : disable port1 of usb2.0 which has two ports. -+ - reg-p1-vbus-supply : regulator of port1's vbus; -+ -+Example: -+ -+u3phy: usb-phy@11271000 { -+ compatible = "mediatek,mt8173-u3phy"; -+ reg = <0 0x11271000 0 0x3000>, -+ <0 0x11280000 0 0x20000>; -+ power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; -+ reg-vusb33-supply = <&mt6397_usb_reg>; -+ clocks = <&perisys PERI_USB0>, -+ <&perisys PERI_USB1>, -+ <&topckgen CLK_TOP_USB30_SEL>, -+ <&apmixedsys CLK_APMIXED_REF2USB_TX>; -+ clock-names = "wakeup_deb_p0", -+ "wakeup_deb_p1", -+ "sys_mac", -+ "u3phya_ref"; -+ disable-usb2-p1; -+}; |