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| author | Koen Vandeputte <koen.vandeputte@ncentric.com> | 2018-05-17 18:41:26 +0200 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2018-05-18 09:10:46 +0200 |
| commit | e2aa0c3f8b49f62fc83ec90f0bc5a67560fffa73 (patch) | |
| tree | 01d46d7549a9554ff8a659993b97b3d07f5e59f1 /target/linux/mvebu/patches-4.14/527-PCI-aardvark-fix-PCIe-max-read-request-size-setting.patch | |
| parent | 12f44b83a8db2c95274839e2e41792e096021f29 (diff) | |
| download | mtk-20170518-e2aa0c3f8b49f62fc83ec90f0bc5a67560fffa73.zip mtk-20170518-e2aa0c3f8b49f62fc83ec90f0bc5a67560fffa73.tar.gz mtk-20170518-e2aa0c3f8b49f62fc83ec90f0bc5a67560fffa73.tar.bz2 | |
kernel: bump 4.14 to 4.14.41
Refreshed all patches
Dropped upstreamed patches:
522-PCI-aardvark-fix-logic-in-PCI-configuration-read-write-functions.patch
523-PCI-aardvark-set-PIO_ADDR_LS-correctly-in-advk_pcie_rd_conf.patch
525-PCI-aardvark-use-isr1-instead-of-isr0-interrupt-in-legacy-irq-mode.patch
527-PCI-aardvark-fix-PCIe-max-read-request-size-setting.patch
updated patches:
524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch
030-USB-serial-option-fix-dwm-158-3g-modem-interface.patch
Added new ARM64 symbol: CONFIG_ARM64_ERRATUM_1024718
Compile-tested on: cns3xxx, imx6, mvebu (arm64), x86_64
Runtime-tested on: cns3xxx, imx6, x86_64
Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
Diffstat (limited to 'target/linux/mvebu/patches-4.14/527-PCI-aardvark-fix-PCIe-max-read-request-size-setting.patch')
| -rw-r--r-- | target/linux/mvebu/patches-4.14/527-PCI-aardvark-fix-PCIe-max-read-request-size-setting.patch | 63 |
1 files changed, 0 insertions, 63 deletions
diff --git a/target/linux/mvebu/patches-4.14/527-PCI-aardvark-fix-PCIe-max-read-request-size-setting.patch b/target/linux/mvebu/patches-4.14/527-PCI-aardvark-fix-PCIe-max-read-request-size-setting.patch deleted file mode 100644 index eaf7b09..0000000 --- a/target/linux/mvebu/patches-4.14/527-PCI-aardvark-fix-PCIe-max-read-request-size-setting.patch +++ /dev/null @@ -1,63 +0,0 @@ -From patchwork Thu Sep 28 12:58:37 2017 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [v2,6/7] PCI: aardvark: fix PCIe max read request size setting -X-Patchwork-Submitter: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> -X-Patchwork-Id: 819591 -Message-Id: <20170928125838.11887-7-thomas.petazzoni@free-electrons.com> -To: Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org -Cc: Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>, - Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Gregory Clement - <gregory.clement@free-electrons.com>, - Nadav Haklai <nadavh@marvell.com>, Hanna Hawa <hannah@marvell.com>, - Yehuda Yitschak <yehuday@marvell.com>, - linux-arm-kernel@lists.infradead.org, Antoine Tenart - <antoine.tenart@free-electrons.com>, =?utf-8?q?Miqu=C3=A8l_Raynal?= - <miquel.raynal@free-electrons.com>, Evan Wang <xswang@marvell.com>, - Thomas Petazzoni <thomas.petazzoni@free-electrons.com> -Date: Thu, 28 Sep 2017 14:58:37 +0200 -From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> -List-Id: <linux-pci.vger.kernel.org> - -From: Evan Wang <xswang@marvell.com> - -There is an obvious typo issue in the definition of the PCIe maximum -read request size: a bit shift is directly used as a value, while it -should be used to shift the correct value. - -This is part of fixing bug -https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was -reported as the user to be important to get a Intel 7260 mini-PCIe -WiFi card working. - -Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver") -Signed-off-by: Evan Wang <xswang@marvell.com> -Reviewed-by: Victor Gu <xigu@marvell.com> -Reviewed-by: Nadav Haklai <nadavh@marvell.com> -[Thomas: tweak commit log.] -Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> ---- - drivers/pci/host/pci-aardvark.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - ---- a/drivers/pci/host/pci-aardvark.c -+++ b/drivers/pci/host/pci-aardvark.c -@@ -33,6 +33,7 @@ - #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2 - #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11) - #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12 -+#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2 - #define PCIE_CORE_MPS_UNIT_BYTE 128 - #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0 - #define PCIE_CORE_LINK_L0S_ENTRY BIT(0) -@@ -303,7 +304,8 @@ static void advk_pcie_setup_hw(struct ad - (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ << - PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) | - PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE | -- PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT; -+ (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ << -+ PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT); - advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG); - - /* Program PCIe Control 2 to disable strict ordering */ |