diff options
author | Henryk Heisig <hyniu@o2.pl> | 2016-09-24 21:41:43 +0200 |
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committer | John Crispin <john@phrozen.org> | 2016-12-22 15:03:30 +0100 |
commit | c8043137bbd323b1490ae8613eab915ba9c138ee (patch) | |
tree | 6ebd7b34943ad84fe7df3a008a03a319ccdf197c /target/linux/ramips/dts | |
parent | 190ee7d86b450083fea4236d588d0d88a50e1311 (diff) | |
download | mtk-20170518-c8043137bbd323b1490ae8613eab915ba9c138ee.zip mtk-20170518-c8043137bbd323b1490ae8613eab915ba9c138ee.tar.gz mtk-20170518-c8043137bbd323b1490ae8613eab915ba9c138ee.tar.bz2 |
ramips: Add support to TP-Link Archer MR200
CPU: MT7620N 580MHz
Flash: 8MB
RAM: 64MB
build-in modem 3G/4G
four ethernet port 10/100Mbps
Signed-off-by: Henryk Heisig <hyniu@o2.pl>
Diffstat (limited to 'target/linux/ramips/dts')
-rw-r--r-- | target/linux/ramips/dts/ArcherMR200.dts | 195 |
1 files changed, 195 insertions, 0 deletions
diff --git a/target/linux/ramips/dts/ArcherMR200.dts b/target/linux/ramips/dts/ArcherMR200.dts new file mode 100644 index 0000000..93fb048 --- /dev/null +++ b/target/linux/ramips/dts/ArcherMR200.dts @@ -0,0 +1,195 @@ +/dts-v1/; + +#include "mt7620a.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "ralink,mt7620a-soc"; + model = "TP-Link Archer MR200"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + lan { + label = "mr200:white:lan"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + + wan { + label = "mr200:white:wan"; + gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + }; + + power { + label = "mr200:white:power"; + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + }; + + 4g { + label = "mr200:white:4g"; + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "mr200:white:wps"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + signal1 { + label = "mr200:white:signal1"; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; + + signal2 { + label = "mr200:white:signal2"; + gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + }; + + signal3 { + label = "mr200:white:signal3"; + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + }; + + signal4 { + label = "mr200:white:signal4"; + gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + }; + + wlan { + label = "mr200:white:wlan"; + gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + reset { + label = "reset"; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_RESTART>; + }; + + rfkill { + label = "rfkill"; + gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_RFKILL>; + }; + }; + + gpio_export { + compatible = "gpio-export"; + #size-cells = <0>; + + power_usb { + gpio-export,name = "power_usb1"; + gpio-export,output = <1>; + gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; + }; + }; + +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + linux,modalias = "m25p80", "mx25l6405d"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x20000>; + read-only; + }; + + partition@20000 { + label = "firmware"; + reg = <0x20000 0x7b0000>; + }; + + rom: partition@7d0000 { + label = "rom"; + reg = <0x7d0000 0x10000>; + read-only; + }; + + partition@7e0000 { + label = "romfile"; + reg = <0x7e0000 0x10000>; + read-only; + }; + + radio: partition@7f0000 { + label = "radio"; + reg = <0x7f0000 0x10000>; + read-only; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "wled", "nd_sd", "ephy", "spi refclk"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&rom 0xf100>; + mediatek,portmap = "llll"; + }; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +&gsw { + mediatek,port4 = "ephy"; +}; + +&wmac { + ralink,mtd-eeprom = <&radio 0>; +}; + +&pcie { + status = "okay"; + + pcie-bridge { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&radio 32768>; + mediatek,2ghz = <0>; + }; + }; +}; |