target/linux : drop ramips/patches-3.10

1 files changed, 0 insertions, 63 deletions

diff --git a/target/linux/ramips/patches-3.10/0016-MIPS-ralink-mt7620-fix-usb-issue-during-frequency-sc.patch b/target/linux/ramips/patches-3.10/0016-MIPS-ralink-mt7620-fix-usb-issue-during-frequency-sc.patch
deleted file mode 100644
index e29bb2b..0000000
--- a/target/linux/ramips/patches-3.10/0016-MIPS-ralink-mt7620-fix-usb-issue-during-frequency-sc.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-From 011f4bdba0dd4d1dff6d33b1a65541fc4f09c78e Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Fri, 24 May 2013 21:28:08 +0200
-Subject: [PATCH 16/25] MIPS: ralink: mt7620: fix usb issue during frequency
- scaling
-
-If the USB HCD is running and the cpu is scaled too low, then the USB stops
-working. Increase the idle speed of the core to fix this if the kernel is
-built with USB support.
-
-The values are taken from the Ralink SDK Kernel.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/include/asm/mach-ralink/mt7620.h |    1 +
- arch/mips/ralink/mt7620.c                  |   19 +++++++++++++++++++
- 2 files changed, 20 insertions(+)
-
---- a/arch/mips/include/asm/mach-ralink/mt7620.h
-+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
-@@ -20,6 +20,7 @@
- #define SYSC_REG_CHIP_REV		0x0c
- #define SYSC_REG_SYSTEM_CONFIG0		0x10
- #define SYSC_REG_SYSTEM_CONFIG1		0x14
-+#define SYSC_REG_CPU_SYS_CLKCFG		0x3c
- #define SYSC_REG_CPLL_CONFIG0		0x54
- #define SYSC_REG_CPLL_CONFIG1		0x58
- 
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -20,6 +20,12 @@
- 
- #include "common.h"
- 
-+/* clock scaling */
-+#define CLKCFG_FDIV_MASK	0x1f00
-+#define CLKCFG_FDIV_USB_VAL	0x0300
-+#define CLKCFG_FFRAC_MASK	0x001f
-+#define CLKCFG_FFRAC_USB_VAL	0x0003
-+
- /* does the board have sdram or ddram */
- static int dram_type;
- 
-@@ -170,6 +176,19 @@ void __init ralink_clk_init(void)
- 	ralink_clk_add("10000500.uart", 40000000);
- 	ralink_clk_add("10000b00.spi", 40000000);
- 	ralink_clk_add("10000c00.uartlite", 40000000);
-+
-+	if (IS_ENABLED(CONFIG_USB)) {
-+		/*
-+		 * When the CPU goes into sleep mode, the BUS clock will be too low for
-+		 * USB to function properly
-+		 */
-+		u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
-+
-+		val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
-+		val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
-+
-+		rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
-+	}
- }
- 
- void __init ralink_of_remap(void)