ramips: sync kernel patches with the mips-next tree

Signed-off-by: John Crispin <blogic@openwrt.org>

SVN-Revision: 36431

1 files changed, 0 insertions, 47 deletions

diff --git a/target/linux/ramips/patches-3.8/0100-MIPS-ralink-fix-RT305x-clock-setup.patch b/target/linux/ramips/patches-3.8/0100-MIPS-ralink-fix-RT305x-clock-setup.patch
deleted file mode 100644
index 55b7532..0000000
--- a/target/linux/ramips/patches-3.8/0100-MIPS-ralink-fix-RT305x-clock-setup.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From eb8d7fbba907df0a51e504930c00b2c9ec837b54 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Fri, 22 Mar 2013 19:25:59 +0100
-Subject: [PATCH 100/121] MIPS: ralink: fix RT305x clock setup
-
-Add a few missing clocks and remove the unused sys clock.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/rt305x.c |   14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/arch/mips/ralink/rt305x.c
-+++ b/arch/mips/ralink/rt305x.c
-@@ -125,6 +125,7 @@ void __init ralink_clk_init(void)
- {
- 	unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
- 	u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
-+	int wmac_20mhz = 0;
- 
- 	if (soc_is_rt305x() || soc_is_rt3350()) {
- 		t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
-@@ -176,11 +177,24 @@ void __init ralink_clk_init(void)
- 		BUG();
- 	}
- 
-+	if (soc_is_rt3352() || soc_is_rt5350()) {
-+		u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
-+		if ((val & RT3352_CLKCFG0_XTAL_SEL) == 0)
-+			wmac_20mhz = 1;
-+	}
-+
- 	ralink_clk_add("cpu", cpu_rate);
- 	ralink_clk_add("10000b00.spi", sys_rate);
- 	ralink_clk_add("10000100.timer", wdt_rate);
-+	ralink_clk_add("10000120.watchdog", wdt_rate);
- 	ralink_clk_add("10000500.uart", uart_rate);
- 	ralink_clk_add("10000c00.uartlite", uart_rate);
-+	ralink_clk_add("10100000.ethernet", sys_rate);
-+
-+	if (wmac_20mhz)
-+		ralink_clk_add("10180000.wmac", 20000000);
-+	else
-+		ralink_clk_add("10180000.wmac", 40000000);
- }
- 
- void __init ralink_of_remap(void)