diff options
author | Felix Fietkau <nbd@nbd.name> | 2016-09-22 16:20:30 +0200 |
---|---|---|
committer | Felix Fietkau <nbd@nbd.name> | 2016-11-14 19:59:32 +0100 |
commit | 4cdbc90a376dd0555201c1434a2081e055e9ceb7 (patch) | |
tree | dd681ea1a0514ecebaa1b1b9f9b105c20d73f8e4 /target/linux/ramips/patches-4.4/100-mt7621-core-detect-hack.patch | |
parent | 913219e6fe65041cd39c9240bfaad0431131fef1 (diff) | |
download | mtk-20170518-4cdbc90a376dd0555201c1434a2081e055e9ceb7.zip mtk-20170518-4cdbc90a376dd0555201c1434a2081e055e9ceb7.tar.gz mtk-20170518-4cdbc90a376dd0555201c1434a2081e055e9ceb7.tar.bz2 |
ramips: add hack to detect missing mt7621 cpu cores
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Diffstat (limited to 'target/linux/ramips/patches-4.4/100-mt7621-core-detect-hack.patch')
-rw-r--r-- | target/linux/ramips/patches-4.4/100-mt7621-core-detect-hack.patch | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-4.4/100-mt7621-core-detect-hack.patch b/target/linux/ramips/patches-4.4/100-mt7621-core-detect-hack.patch new file mode 100644 index 0000000..4049d13 --- /dev/null +++ b/target/linux/ramips/patches-4.4/100-mt7621-core-detect-hack.patch @@ -0,0 +1,61 @@ +There is a variant of MT7621 which contains only one CPU core instead of 2. +This is not reflected in the config register, so the kernel detects more +physical cores, which leads to a hang on SMP bringup. +Add a hack to detect missing cores. + +Signed-off-by: Felix Fietkau <nbd@nbd.name> + +--- a/arch/mips/kernel/smp-cps.c ++++ b/arch/mips/kernel/smp-cps.c +@@ -44,6 +44,11 @@ static unsigned core_vpe_count(unsigned + return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1; + } + ++bool __weak plat_cpu_core_present(int core) ++{ ++ return true; ++} ++ + static void __init cps_smp_setup(void) + { + unsigned int ncores, nvpes, core_vpes; +@@ -53,6 +58,8 @@ static void __init cps_smp_setup(void) + ncores = mips_cm_numcores(); + pr_info("VPE topology "); + for (c = nvpes = 0; c < ncores; c++) { ++ if (!plat_cpu_core_present(c)) ++ continue; + core_vpes = core_vpe_count(c); + pr_cont("%c%u", c ? ',' : '{', core_vpes); + +--- a/arch/mips/ralink/mt7621.c ++++ b/arch/mips/ralink/mt7621.c +@@ -20,6 +20,7 @@ + #include <asm/mips-cpc.h> + #include <asm/mach-ralink/ralink_regs.h> + #include <asm/mach-ralink/mt7621.h> ++#include <asm/mips-boards/launch.h> + + #include <pinmux.h> + +@@ -163,6 +164,20 @@ void __init ralink_of_remap(void) + panic("Failed to remap core resources"); + } + ++bool plat_cpu_core_present(int core) ++{ ++ struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); ++ ++ if (!core) ++ return true; ++ launch += core * 2; /* 2 VPEs per core */ ++ if (!(launch->flags & LAUNCH_FREADY)) ++ return false; ++ if (launch->flags & (LAUNCH_FGO | LAUNCH_FGONE)) ++ return false; ++ return true; ++} ++ + void prom_soc_init(struct ralink_soc_info *soc_info) + { + void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE); |