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author | Florian Fainelli <florian@openwrt.org> | 2008-06-28 11:07:07 +0000 |
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committer | Florian Fainelli <florian@openwrt.org> | 2008-06-28 11:07:07 +0000 |
commit | 310c6108cd662e1f5b65c09f41f59cb3f7aeba49 (patch) | |
tree | 99c59aedf82224b8a87d539419b5814e61b4a60a /target/linux/rdc/files/arch/x86/mach-rdc/gpio.c | |
parent | 9e151671a9080263eaf64a3369ece974f196b481 (diff) | |
download | mtk-20170518-310c6108cd662e1f5b65c09f41f59cb3f7aeba49.zip mtk-20170518-310c6108cd662e1f5b65c09f41f59cb3f7aeba49.tar.gz mtk-20170518-310c6108cd662e1f5b65c09f41f59cb3f7aeba49.tar.bz2 |
Put back 2.6.24 files as well
SVN-Revision: 11593
Diffstat (limited to 'target/linux/rdc/files/arch/x86/mach-rdc/gpio.c')
-rw-r--r-- | target/linux/rdc/files/arch/x86/mach-rdc/gpio.c | 91 |
1 files changed, 91 insertions, 0 deletions
diff --git a/target/linux/rdc/files/arch/x86/mach-rdc/gpio.c b/target/linux/rdc/files/arch/x86/mach-rdc/gpio.c new file mode 100644 index 0000000..dbd0327 --- /dev/null +++ b/target/linux/rdc/files/arch/x86/mach-rdc/gpio.c @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2007, OpenWrt.org, Florian Fainelli <florian@openwrt.org> + * RDC321x architecture specific GPIO support + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <linux/autoconf.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/types.h> +#include <linux/module.h> +#include <linux/delay.h> + +#include <asm/mach-rdc/rdc321x_defs.h> + +static inline int rdc_gpio_is_valid(unsigned gpio) +{ + return (gpio <= RDC_MAX_GPIO); +} + +static unsigned int rdc_gpio_read(unsigned gpio) +{ + unsigned int val; + + val = 0x80000000 | (7 << 11) | ((gpio&0x20?0x84:0x48)); + outl(val, RDC3210_CFGREG_ADDR); + udelay(10); + val = inl(RDC3210_CFGREG_DATA); + val |= (0x1 << (gpio & 0x1F)); + outl(val, RDC3210_CFGREG_DATA); + udelay(10); + val = 0x80000000 | (7 << 11) | ((gpio&0x20?0x88:0x4C)); + outl(val, RDC3210_CFGREG_ADDR); + udelay(10); + val = inl(RDC3210_CFGREG_DATA); + + return val; +} + +static void rdc_gpio_write(unsigned int val) +{ + if (val) { + outl(val, RDC3210_CFGREG_DATA); + udelay(10); + } +} + +int rdc_gpio_get_value(unsigned gpio) +{ + if (rdc_gpio_is_valid(gpio)) + return (int)rdc_gpio_read(gpio); + else + return -EINVAL; +} +EXPORT_SYMBOL(rdc_gpio_get_value); + +void rdc_gpio_set_value(unsigned gpio, int value) +{ + unsigned int val; + + if (!rdc_gpio_is_valid(gpio)) + return; + + val = rdc_gpio_read(gpio); + + if (value) + val &= ~(0x1 << (gpio & 0x1F)); + else + val |= (0x1 << (gpio & 0x1F)); + + rdc_gpio_write(val); +} +EXPORT_SYMBOL(rdc_gpio_set_value); + +int rdc_gpio_direction_input(unsigned gpio) +{ + return 0; +} +EXPORT_SYMBOL(rdc_gpio_direction_input); + +int rdc_gpio_direction_output(unsigned gpio, int value) +{ + return 0; +} +EXPORT_SYMBOL(rdc_gpio_direction_output); + + |