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authorZoltan Herpai <wigyori@uid0.hu>2014-03-05 23:19:25 +0000
committerZoltan Herpai <wigyori@uid0.hu>2014-03-05 23:19:25 +0000
commit301baf34ddbc838b61dfd8564b27a440f0b85e5a (patch)
treee676718f90241c41d5dc1da4b8a94eba0ab3fddd /target/linux/sunxi/patches-3.12/101-clk-sunxi_add-gating-pll1.patch
parent6892ed8193e8a195a6b5302bb55b24acdbf79abc (diff)
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sunxi: deprecate 3.12 support
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu> SVN-Revision: 39780
Diffstat (limited to 'target/linux/sunxi/patches-3.12/101-clk-sunxi_add-gating-pll1.patch')
-rw-r--r--target/linux/sunxi/patches-3.12/101-clk-sunxi_add-gating-pll1.patch51
1 files changed, 0 insertions, 51 deletions
diff --git a/target/linux/sunxi/patches-3.12/101-clk-sunxi_add-gating-pll1.patch b/target/linux/sunxi/patches-3.12/101-clk-sunxi_add-gating-pll1.patch
deleted file mode 100644
index 00519b8..0000000
--- a/target/linux/sunxi/patches-3.12/101-clk-sunxi_add-gating-pll1.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From 68557a66b206de79a4556d393d51865407525d52 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Mon, 6 May 2013 09:59:00 -0300
-Subject: [PATCH] clk: sunxi: add gating support to PLL1
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This commit adds gating support to PLL1 on the clock driver. This makes
-the PLL1 implementation fully compatible with PLL4 as well.
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
----
- Documentation/devicetree/bindings/clock/sunxi.txt | 2 +-
- drivers/clk/sunxi/clk-sunxi.c | 2 ++
- 2 files changed, 3 insertions(+), 1 deletion(-)
-
-diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
-index 00a5c264..7d9245f 100644
---- a/Documentation/devicetree/bindings/clock/sunxi.txt
-+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
-@@ -7,7 +7,7 @@ This binding uses the common clock binding[1].
- Required properties:
- - compatible : shall be one of the following:
- "allwinner,sun4i-osc-clk" - for a gatable oscillator
-- "allwinner,sun4i-pll1-clk" - for the main PLL clock
-+ "allwinner,sun4i-pll1-clk" - for the main PLL clock and PLL4
- "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
- "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
- "allwinner,sun4i-axi-clk" - for the AXI clock
-diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
-index 6aed57f..c0b0675 100644
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -293,11 +293,13 @@ struct factors_data {
- };
-
- static const struct factors_data sun4i_pll1_data __initconst = {
-+ .enable = 31,
- .table = &sun4i_pll1_config,
- .getter = sun4i_get_pll1_factors,
- };
-
- static const struct factors_data sun6i_a31_pll1_data __initconst = {
-+ .enable = 31,
- .table = &sun6i_a31_pll1_config,
- .getter = sun6i_a31_get_pll1_factors,
- };
---
-1.8.4
-