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author | Lars-Peter Clausen <lars@metafoo.de> | 2010-01-11 04:44:45 +0000 |
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committer | Lars-Peter Clausen <lars@metafoo.de> | 2010-01-11 04:44:45 +0000 |
commit | 541158d5ad4a941d927a397737b6588d2e4db22d (patch) | |
tree | e49a97f18123413611824b8993e9acff9d681bae /target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/head.S | |
parent | db06ca593b3d80ec514ecb2b20d49e3638cd3f0b (diff) | |
download | mtk-20170518-541158d5ad4a941d927a397737b6588d2e4db22d.zip mtk-20170518-541158d5ad4a941d927a397737b6588d2e4db22d.tar.gz mtk-20170518-541158d5ad4a941d927a397737b6588d2e4db22d.tar.bz2 |
Merge xburst target.
SVN-Revision: 19098
Diffstat (limited to 'target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/head.S')
-rw-r--r-- | target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/head.S | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/head.S b/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/head.S new file mode 100644 index 0000000..d9700eb --- /dev/null +++ b/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/head.S @@ -0,0 +1,85 @@ +/* + * linux/arch/mips/boot/compressed/head.S + * + * Copyright (C) 2005-2008 Ingenic Semiconductor Inc. + */ + +#include <asm/asm.h> +#include <asm/cacheops.h> +#include <asm/cachectl.h> +#include <asm/regdef.h> + +#define IndexInvalidate_I 0x00 +#define IndexWriteBack_D 0x01 + + .set noreorder + LEAF(startup) +startup: + move s0, a0 /* Save the boot loader transfered args */ + move s1, a1 + move s2, a2 + move s3, a3 + + la a0, _edata + la a1, _end +1: sw zero, 0(a0) /* Clear BSS section */ + bne a1, a0, 1b + addu a0, 4 + + la sp, (.stack + 8192) + + la a0, __image_begin + la a1, IMAGESIZE + la a2, LOADADDR + la ra, 1f + la k0, decompress_kernel + jr k0 + nop +1: + + move a0, s0 + move a1, s1 + move a2, s2 + move a3, s3 + li k0, KERNEL_ENTRY + jr k0 + nop +2: + b 32 + END(startup) + + + LEAF(flushcaches) + la t0, 1f + la t1, 0xa0000000 + or t0, t0, t1 + jr t0 + nop +1: + li k0, 0x80000000 # start address + li k1, 0x80004000 # end address (16KB I-Cache) + subu k1, 128 + +2: + .set mips3 + cache IndexWriteBack_D, 0(k0) + cache IndexWriteBack_D, 32(k0) + cache IndexWriteBack_D, 64(k0) + cache IndexWriteBack_D, 96(k0) + cache IndexInvalidate_I, 0(k0) + cache IndexInvalidate_I, 32(k0) + cache IndexInvalidate_I, 64(k0) + cache IndexInvalidate_I, 96(k0) + .set mips0 + + bne k0, k1, 2b + addu k0, k0, 128 + la t0, 3f + jr t0 + nop +3: + jr ra + nop + END(flushcaches) + + .comm .stack,4096*2,4 |