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authorGabor Juhos <juhosg@openwrt.org>2009-03-14 19:28:28 +0000
committerGabor Juhos <juhosg@openwrt.org>2009-03-14 19:28:28 +0000
commit9b594998930dcb047f989544288dc828053bea28 (patch)
tree6685b94fca029253fd4adb2702851b550ea682f9 /target/linux
parentfa36af494f00c64f1dedbc3573113c3abbd2c239 (diff)
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mtk-20170518-9b594998930dcb047f989544288dc828053bea28.tar.gz
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pb42: add GPIO buttons
SVN-Revision: 14877
Diffstat (limited to 'target/linux')
-rw-r--r--target/linux/ar71xx/files/arch/mips/ar71xx/mach-pb42.c28
1 files changed, 28 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/mach-pb42.c b/target/linux/ar71xx/files/arch/mips/ar71xx/mach-pb42.c
index 67efe8f..154a1e4 100644
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/mach-pb42.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/mach-pb42.c
@@ -11,6 +11,7 @@
#include <linux/init.h>
#include <linux/bitops.h>
+#include <linux/input.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
@@ -21,6 +22,11 @@
#include "devices.h"
+#define PB42_BUTTONS_POLL_INTERVAL 20
+
+#define PB42_GPIO_BTN_SW4 8
+#define PB42_GPIO_BTN_SW5 3
+
static struct spi_board_info pb42_spi_info[] = {
{
.bus_num = 0,
@@ -46,6 +52,24 @@ static struct ar71xx_pci_irq pb42_pci_irqs[] __initdata = {
}
};
+static struct gpio_button pb42_gpio_buttons[] __initdata = {
+ {
+ .desc = "sw4",
+ .type = EV_KEY,
+ .code = BTN_0,
+ .threshold = 5,
+ .gpio = PB42_GPIO_BTN_SW4,
+ .active_low = 1,
+ } , {
+ .desc = "sw5",
+ .type = EV_KEY,
+ .code = BTN_1,
+ .threshold = 5,
+ .gpio = PB42_GPIO_BTN_SW5,
+ .active_low = 1,
+ }
+};
+
#define PB42_WAN_PHYMASK BIT(20)
#define PB42_LAN_PHYMASK (BIT(16) | BIT(17) | BIT(18) | BIT(19))
#define PB42_MDIO_PHYMASK (PB42_LAN_PHYMASK | PB42_WAN_PHYMASK)
@@ -68,6 +92,10 @@ static void __init pb42_init(void)
ar71xx_add_device_eth(0);
ar71xx_add_device_eth(1);
+ ar71xx_add_device_gpio_buttons(-1, PB42_BUTTONS_POLL_INTERVAL,
+ ARRAY_SIZE(pb42_gpio_buttons),
+ pb42_gpio_buttons);
+
ar71xx_pci_init(ARRAY_SIZE(pb42_pci_irqs), pb42_pci_irqs);
}