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authorFelix Fietkau <nbd@nbd.name>2017-02-17 11:51:42 +0100
committerFelix Fietkau <nbd@nbd.name>2017-02-17 12:16:13 +0100
commit72327d1757b53d36e97282451d3c4d10d99adfc8 (patch)
tree3354c8284bd21d90c7987f4736f2c1ff62a73218 /target
parentd6baeb5c480f547f13f92b8994cf467d25e2ef7e (diff)
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ar71xx: fix ethernet PLL configuration for QCA956x
QCA956x is configured like AR934x, not like the older chips. Should fix ethernet hangs when using the WAN port without SGMII Signed-off-by: Felix Fietkau <nbd@nbd.name>
Diffstat (limited to 'target')
-rw-r--r--target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
index 91ff8b2..a8b19b6 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
@@ -1096,7 +1096,7 @@ void __init ath79_register_eth(unsigned int id)
if (pdata->phy_if_mode == PHY_INTERFACE_MODE_SGMII)
pdata->set_speed = qca956x_set_speed_sgmii;
else
- pdata->set_speed = ath79_set_speed_ge0;
+ pdata->set_speed = ar934x_set_speed_ge0;
} else {
pdata->reset_bit = QCA955X_RESET_GE1_MAC |
QCA955X_RESET_GE1_MDIO;