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| author | Gabor Juhos <juhosg@openwrt.org> | 2012-08-02 09:54:28 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2012-08-02 09:54:28 +0000 |
| commit | 79a8660d679b711598794dfab9f1bebe390dfac4 (patch) | |
| tree | b104a6ca5c5b7f16ec25487aeeedc76e014ccdc1 /target | |
| parent | e2782eae8ee17143d0506078fcf5c0a44b2302fe (diff) | |
| download | mtk-20170518-79a8660d679b711598794dfab9f1bebe390dfac4.zip mtk-20170518-79a8660d679b711598794dfab9f1bebe390dfac4.tar.gz mtk-20170518-79a8660d679b711598794dfab9f1bebe390dfac4.tar.bz2 | |
ar71xx: init switch hw_reset on the TL-WR1043ND board
SVN-Revision: 32944
Diffstat (limited to 'target')
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd.c | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd.c index e789b40..61aeb52 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd.c @@ -10,7 +10,9 @@ #include <linux/platform_device.h> #include <linux/rtl8366.h> + #include <asm/mach-ath79/ath79.h> +#include <asm/mach-ath79/ar71xx_regs.h> #include "dev-eth.h" #include "dev-m25p80.h" @@ -81,9 +83,18 @@ static struct gpio_keys_button tl_wr1043nd_gpio_keys[] __initdata = { } }; +static void tl_wr1043nd_rtl8366rb_hw_reset(bool active) +{ + if (active) + ath79_device_reset_set(AR71XX_RESET_GE0_PHY); + else + ath79_device_reset_clear(AR71XX_RESET_GE0_PHY); +} + static struct rtl8366_platform_data tl_wr1043nd_rtl8366rb_data = { - .gpio_sda = TL_WR1043ND_GPIO_RTL8366_SDA, - .gpio_sck = TL_WR1043ND_GPIO_RTL8366_SCK, + .gpio_sda = TL_WR1043ND_GPIO_RTL8366_SDA, + .gpio_sck = TL_WR1043ND_GPIO_RTL8366_SCK, + .hw_reset = tl_wr1043nd_rtl8366rb_hw_reset, }; static struct platform_device tl_wr1043nd_rtl8366rb_device = { @@ -99,6 +110,8 @@ static void __init tl_wr1043nd_setup(void) u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + tl_wr1043nd_rtl8366rb_hw_reset(true); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); ath79_eth0_data.mii_bus_dev = &tl_wr1043nd_rtl8366rb_device.dev; ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; |