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author | Gabor Juhos <juhosg@openwrt.org> | 2013-10-30 07:06:23 +0000 |
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committer | Gabor Juhos <juhosg@openwrt.org> | 2013-10-30 07:06:23 +0000 |
commit | dfd43113552598a8b519da43583d19dee2f99403 (patch) | |
tree | 511815d3502491efa6f656921a7d3d7166f413a7 /target | |
parent | 9186fb342e4d29f4e58bf10ad1cc86a4ae40261f (diff) | |
download | mtk-20170518-dfd43113552598a8b519da43583d19dee2f99403.zip mtk-20170518-dfd43113552598a8b519da43583d19dee2f99403.tar.gz mtk-20170518-dfd43113552598a8b519da43583d19dee2f99403.tar.bz2 |
ramips: fix number of GPIOs for RT3352
The RT3352 SoC only supports 46 GPIO lines.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 38602
Diffstat (limited to 'target')
-rw-r--r-- | target/linux/ramips/dts/rt3352.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/linux/ramips/dts/rt3352.dtsi b/target/linux/ramips/dts/rt3352.dtsi index ca81bb6..6b1f11d 100644 --- a/target/linux/ramips/dts/rt3352.dtsi +++ b/target/linux/ramips/dts/rt3352.dtsi @@ -132,7 +132,7 @@ #gpio-cells = <2>; ralink,gpio-base = <40>; - ralink,num-gpios = <12>; + ralink,num-gpios = <6>; ralink,register-map = [ 00 04 08 0c 10 14 18 1c 20 24 ]; |