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Diffstat (limited to 'target/linux/brcm47xx/patches-3.10/159-cpu_fixes.patch')
-rw-r--r--target/linux/brcm47xx/patches-3.10/159-cpu_fixes.patch368
1 files changed, 0 insertions, 368 deletions
diff --git a/target/linux/brcm47xx/patches-3.10/159-cpu_fixes.patch b/target/linux/brcm47xx/patches-3.10/159-cpu_fixes.patch
deleted file mode 100644
index 984624a..0000000
--- a/target/linux/brcm47xx/patches-3.10/159-cpu_fixes.patch
+++ /dev/null
@@ -1,368 +0,0 @@
---- a/arch/mips/include/asm/r4kcache.h
-+++ b/arch/mips/include/asm/r4kcache.h
-@@ -17,6 +17,20 @@
- #include <asm/cpu-features.h>
- #include <asm/mipsmtregs.h>
-
-+#ifdef CONFIG_BCM47XX
-+#include <asm/paccess.h>
-+#include <linux/ssb/ssb.h>
-+#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE)))
-+
-+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
-+#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
-+#else
-+#define BCM4710_DUMMY_RREG()
-+
-+#define BCM4710_FILL_TLB(addr)
-+#define BCM4710_PROTECTED_FILL_TLB(addr)
-+#endif
-+
- /*
- * This macro return a properly sign-extended address suitable as base address
- * for indexed cache operations. Two issues here:
-@@ -150,6 +164,7 @@ static inline void flush_icache_line_ind
- static inline void flush_dcache_line_indexed(unsigned long addr)
- {
- __dflush_prologue
-+ BCM4710_DUMMY_RREG();
- cache_op(Index_Writeback_Inv_D, addr);
- __dflush_epilogue
- }
-@@ -169,6 +184,7 @@ static inline void flush_icache_line(uns
- static inline void flush_dcache_line(unsigned long addr)
- {
- __dflush_prologue
-+ BCM4710_DUMMY_RREG();
- cache_op(Hit_Writeback_Inv_D, addr);
- __dflush_epilogue
- }
-@@ -176,6 +192,7 @@ static inline void flush_dcache_line(uns
- static inline void invalidate_dcache_line(unsigned long addr)
- {
- __dflush_prologue
-+ BCM4710_DUMMY_RREG();
- cache_op(Hit_Invalidate_D, addr);
- __dflush_epilogue
- }
-@@ -208,6 +225,7 @@ static inline void flush_scache_line(uns
- */
- static inline void protected_flush_icache_line(unsigned long addr)
- {
-+ BCM4710_DUMMY_RREG();
- protected_cache_op(Hit_Invalidate_I, addr);
- }
-
-@@ -219,6 +237,7 @@ static inline void protected_flush_icach
- */
- static inline void protected_writeback_dcache_line(unsigned long addr)
- {
-+ BCM4710_DUMMY_RREG();
- protected_cache_op(Hit_Writeback_Inv_D, addr);
- }
-
-@@ -339,8 +358,52 @@ static inline void invalidate_tcache_pag
- : "r" (base), \
- "i" (op));
-
-+static inline void blast_dcache(void)
-+{
-+ unsigned long start = KSEG0;
-+ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
-+ unsigned long end = (start + dcache_size);
-+
-+ do {
-+ BCM4710_DUMMY_RREG();
-+ cache_op(Index_Writeback_Inv_D, start);
-+ start += current_cpu_data.dcache.linesz;
-+ } while(start < end);
-+}
-+
-+static inline void blast_dcache_page(unsigned long page)
-+{
-+ unsigned long start = page;
-+ unsigned long end = start + PAGE_SIZE;
-+
-+ BCM4710_FILL_TLB(start);
-+ do {
-+ BCM4710_DUMMY_RREG();
-+ cache_op(Hit_Writeback_Inv_D, start);
-+ start += current_cpu_data.dcache.linesz;
-+ } while(start < end);
-+}
-+
-+static inline void blast_dcache_page_indexed(unsigned long page)
-+{
-+ unsigned long start = page;
-+ unsigned long end = start + PAGE_SIZE;
-+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
-+ unsigned long ws_end = current_cpu_data.dcache.ways <<
-+ current_cpu_data.dcache.waybit;
-+ unsigned long ws, addr;
-+ for (ws = 0; ws < ws_end; ws += ws_inc) {
-+ start = page + ws;
-+ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
-+ BCM4710_DUMMY_RREG();
-+ cache_op(Index_Writeback_Inv_D, addr);
-+ }
-+ }
-+}
-+
-+
- /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
--#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
-+#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, war) \
- static inline void blast_##pfx##cache##lsize(void) \
- { \
- unsigned long start = INDEX_BASE; \
-@@ -352,6 +415,7 @@ static inline void blast_##pfx##cache##l
- \
- __##pfx##flush_prologue \
- \
-+ war \
- for (ws = 0; ws < ws_end; ws += ws_inc) \
- for (addr = start; addr < end; addr += lsize * 32) \
- cache##lsize##_unroll32(addr|ws, indexop); \
-@@ -366,6 +430,7 @@ static inline void blast_##pfx##cache##l
- \
- __##pfx##flush_prologue \
- \
-+ war \
- do { \
- cache##lsize##_unroll32(start, hitop); \
- start += lsize * 32; \
-@@ -384,6 +449,8 @@ static inline void blast_##pfx##cache##l
- current_cpu_data.desc.waybit; \
- unsigned long ws, addr; \
- \
-+ war \
-+ \
- __##pfx##flush_prologue \
- \
- for (ws = 0; ws < ws_end; ws += ws_inc) \
-@@ -393,36 +460,38 @@ static inline void blast_##pfx##cache##l
- __##pfx##flush_epilogue \
- }
-
--__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
--__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
--__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64)
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
--
--__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
--__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
--__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16)
--__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32)
--__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64)
--__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
-+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
-+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
-+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
-+
-+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
-+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
-+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
-+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
-+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
-+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
-
- /* build blast_xxx_range, protected_blast_xxx_range */
--#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
-+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war, war2) \
- static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
- unsigned long end) \
- { \
- unsigned long lsize = cpu_##desc##_line_size(); \
- unsigned long addr = start & ~(lsize - 1); \
- unsigned long aend = (end - 1) & ~(lsize - 1); \
-+ war \
- \
- __##pfx##flush_prologue \
- \
- while (1) { \
-+ war2 \
- prot##cache_op(hitop, addr); \
- if (addr == aend) \
- break; \
-@@ -432,13 +501,13 @@ static inline void prot##blast_##pfx##ca
- __##pfx##flush_epilogue \
- }
-
--__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
--__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
--__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
--__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
--__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
-+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
-+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_,, )
-+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_,, )
-+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D,, BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
-+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD,,, )
- /* blast_inv_dcache_range */
--__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
--__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
-+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D,,,BCM4710_DUMMY_RREG();)
-+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
-
- #endif /* _ASM_R4KCACHE_H */
---- a/arch/mips/include/asm/stackframe.h
-+++ b/arch/mips/include/asm/stackframe.h
-@@ -449,6 +449,10 @@
- .macro RESTORE_SP_AND_RET
- LONG_L sp, PT_R29(sp)
- .set mips3
-+#ifdef CONFIG_BCM47XX
-+ nop
-+ nop
-+#endif
- eret
- .set mips0
- .endm
---- a/arch/mips/kernel/genex.S
-+++ b/arch/mips/kernel/genex.S
-@@ -46,6 +46,10 @@
- NESTED(except_vec3_generic, 0, sp)
- .set push
- .set noat
-+#ifdef CONFIG_BCM47XX
-+ nop
-+ nop
-+#endif
- #if R5432_CP0_INTERRUPT_WAR
- mfc0 k0, CP0_INDEX
- #endif
---- a/arch/mips/mm/c-r4k.c
-+++ b/arch/mips/mm/c-r4k.c
-@@ -35,6 +35,9 @@
- #include <asm/traps.h>
- #include <asm/dma-coherence.h>
-
-+/* For enabling BCM4710 cache workarounds */
-+int bcm4710 = 0;
-+
- /*
- * Special Variant of smp_call_function for use by cache functions:
- *
-@@ -111,6 +114,9 @@ static void __cpuinit r4k_blast_dcache_p
- {
- unsigned long dc_lsize = cpu_dcache_line_size();
-
-+ if (bcm4710)
-+ r4k_blast_dcache_page = blast_dcache_page;
-+ else
- if (dc_lsize == 0)
- r4k_blast_dcache_page = (void *)cache_noop;
- else if (dc_lsize == 16)
-@@ -127,6 +133,9 @@ static void __cpuinit r4k_blast_dcache_p
- {
- unsigned long dc_lsize = cpu_dcache_line_size();
-
-+ if (bcm4710)
-+ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
-+ else
- if (dc_lsize == 0)
- r4k_blast_dcache_page_indexed = (void *)cache_noop;
- else if (dc_lsize == 16)
-@@ -144,6 +153,9 @@ static void __cpuinit r4k_blast_dcache_s
- {
- unsigned long dc_lsize = cpu_dcache_line_size();
-
-+ if (bcm4710)
-+ r4k_blast_dcache = blast_dcache;
-+ else
- if (dc_lsize == 0)
- r4k_blast_dcache = (void *)cache_noop;
- else if (dc_lsize == 16)
-@@ -674,6 +686,8 @@ static void local_r4k_flush_cache_sigtra
- unsigned long addr = (unsigned long) arg;
-
- R4600_HIT_CACHEOP_WAR_IMPL;
-+ BCM4710_PROTECTED_FILL_TLB(addr);
-+ BCM4710_PROTECTED_FILL_TLB(addr + 4);
- if (dc_lsize)
- protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
- if (!cpu_icache_snoops_remote_store && scache_size)
-@@ -1357,6 +1371,17 @@ static void __cpuinit coherency_setup(vo
- * silly idea of putting something else there ...
- */
- switch (current_cpu_type()) {
-+ case CPU_BMIPS3300:
-+ {
-+ u32 cm;
-+ cm = read_c0_diag();
-+ /* Enable icache */
-+ cm |= (1 << 31);
-+ /* Enable dcache */
-+ cm |= (1 << 30);
-+ write_c0_diag(cm);
-+ }
-+ break;
- case CPU_R4000PC:
- case CPU_R4000SC:
- case CPU_R4000MC:
-@@ -1404,6 +1429,15 @@ void __cpuinit r4k_cache_init(void)
- extern void build_copy_page(void);
- struct cpuinfo_mips *c = &current_cpu_data;
-
-+ /* Check if special workarounds are required */
-+#ifdef CONFIG_BCM47XX
-+ if (current_cpu_data.cputype == CPU_BMIPS32 && (current_cpu_data.processor_id & 0xff) == 0) {
-+ printk("Enabling BCM4710A0 cache workarounds.\n");
-+ bcm4710 = 1;
-+ } else
-+#endif
-+ bcm4710 = 0;
-+
- probe_pcache();
- setup_scache();
-
-@@ -1469,6 +1503,14 @@ void __cpuinit r4k_cache_init(void)
- */
- local_r4k___flush_cache_all(NULL);
-
-+#ifdef CONFIG_BCM47XX
-+ {
-+ static void (*_coherency_setup)(void);
-+ _coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
-+ _coherency_setup();
-+ }
-+#else
- coherency_setup();
-+#endif
- board_cache_error_setup = r4k_cache_error_setup;
- }
---- a/arch/mips/mm/tlbex.c
-+++ b/arch/mips/mm/tlbex.c
-@@ -1311,6 +1311,9 @@ static void __cpuinit build_r4000_tlb_re
- /* No need for uasm_i_nop */
- }
-
-+#ifdef CONFIG_BCM47XX
-+ uasm_i_nop(&p);
-+#endif
- #ifdef CONFIG_64BIT
- build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
- #else
-@@ -1842,6 +1845,9 @@ build_r4000_tlbchange_handler_head(u32 *
- {
- struct work_registers wr = build_get_work_registers(p);
-
-+#ifdef CONFIG_BCM47XX
-+ uasm_i_nop(p);
-+#endif
- #ifdef CONFIG_64BIT
- build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
- #else
generated by cgit v1.1 at 2024-11-21 22:33:33 +0000