diff options
Diffstat (limited to 'target/linux/generic/patches-3.10/025-bcma_backport.patch')
| -rw-r--r-- | target/linux/generic/patches-3.10/025-bcma_backport.patch | 1768 |
1 files changed, 0 insertions, 1768 deletions
diff --git a/target/linux/generic/patches-3.10/025-bcma_backport.patch b/target/linux/generic/patches-3.10/025-bcma_backport.patch deleted file mode 100644 index 0d41ed0..0000000 --- a/target/linux/generic/patches-3.10/025-bcma_backport.patch +++ /dev/null @@ -1,1768 +0,0 @@ ---- a/drivers/bcma/Kconfig -+++ b/drivers/bcma/Kconfig -@@ -26,6 +26,7 @@ config BCMA_HOST_PCI_POSSIBLE - config BCMA_HOST_PCI - bool "Support for BCMA on PCI-host bus" - depends on BCMA_HOST_PCI_POSSIBLE -+ default y - - config BCMA_DRIVER_PCI_HOSTMODE - bool "Driver for PCI core working in hostmode" -@@ -34,8 +35,14 @@ config BCMA_DRIVER_PCI_HOSTMODE - PCI core hostmode operation (external PCI bus). - - config BCMA_HOST_SOC -- bool -- depends on BCMA_DRIVER_MIPS -+ bool "Support for BCMA in a SoC" -+ depends on BCMA -+ help -+ Host interface for a Broadcom AIX bus directly mapped into -+ the memory. This only works with the Broadcom SoCs from the -+ BCM47XX line. -+ -+ If unsure, say N - - config BCMA_DRIVER_MIPS - bool "BCMA Broadcom MIPS core driver" -@@ -68,6 +75,7 @@ config BCMA_DRIVER_GMAC_CMN - config BCMA_DRIVER_GPIO - bool "BCMA GPIO driver" - depends on BCMA && GPIOLIB -+ select IRQ_DOMAIN if BCMA_HOST_SOC - help - Driver to provide access to the GPIO pins of the bcma bus. - ---- a/drivers/bcma/Makefile -+++ b/drivers/bcma/Makefile -@@ -3,6 +3,7 @@ bcma-y += driver_chipcommon.o driver - bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o - bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o - bcma-y += driver_pci.o -+bcma-y += driver_pcie2.o - bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o - bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o - bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o ---- a/drivers/bcma/bcma_private.h -+++ b/drivers/bcma/bcma_private.h -@@ -22,6 +22,8 @@ - struct bcma_bus; - - /* main.c */ -+bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value, -+ int timeout); - int bcma_bus_register(struct bcma_bus *bus); - void bcma_bus_unregister(struct bcma_bus *bus); - int __init bcma_bus_early_register(struct bcma_bus *bus, -@@ -31,8 +33,6 @@ int __init bcma_bus_early_register(struc - int bcma_bus_suspend(struct bcma_bus *bus); - int bcma_bus_resume(struct bcma_bus *bus); - #endif --struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid, -- u8 unit); - - /* scan.c */ - int bcma_bus_scan(struct bcma_bus *bus); ---- a/drivers/bcma/core.c -+++ b/drivers/bcma/core.c -@@ -9,6 +9,25 @@ - #include <linux/export.h> - #include <linux/bcma/bcma.h> - -+static bool bcma_core_wait_value(struct bcma_device *core, u16 reg, u32 mask, -+ u32 value, int timeout) -+{ -+ unsigned long deadline = jiffies + timeout; -+ u32 val; -+ -+ do { -+ val = bcma_aread32(core, reg); -+ if ((val & mask) == value) -+ return true; -+ cpu_relax(); -+ udelay(10); -+ } while (!time_after_eq(jiffies, deadline)); -+ -+ bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg); -+ -+ return false; -+} -+ - bool bcma_core_is_enabled(struct bcma_device *core) - { - if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC)) -@@ -25,13 +44,15 @@ void bcma_core_disable(struct bcma_devic - if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET) - return; - -- bcma_awrite32(core, BCMA_IOCTL, flags); -- bcma_aread32(core, BCMA_IOCTL); -- udelay(10); -+ bcma_core_wait_value(core, BCMA_RESET_ST, ~0, 0, 300); - - bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET); - bcma_aread32(core, BCMA_RESET_CTL); - udelay(1); -+ -+ bcma_awrite32(core, BCMA_IOCTL, flags); -+ bcma_aread32(core, BCMA_IOCTL); -+ udelay(10); - } - EXPORT_SYMBOL_GPL(bcma_core_disable); - -@@ -43,6 +64,7 @@ int bcma_core_enable(struct bcma_device - bcma_aread32(core, BCMA_IOCTL); - - bcma_awrite32(core, BCMA_RESET_CTL, 0); -+ bcma_aread32(core, BCMA_RESET_CTL); - udelay(1); - - bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags)); ---- a/drivers/bcma/driver_chipcommon.c -+++ b/drivers/bcma/driver_chipcommon.c -@@ -140,8 +140,15 @@ void bcma_core_chipcommon_init(struct bc - bcma_core_chipcommon_early_init(cc); - - if (cc->core->id.rev >= 20) { -- bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0); -- bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0); -+ u32 pullup = 0, pulldown = 0; -+ -+ if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) { -+ pullup = 0x402e0; -+ pulldown = 0x20500; -+ } -+ -+ bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup); -+ bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown); - } - - if (cc->capabilities & BCMA_CC_CAP_PMU) ---- a/drivers/bcma/driver_chipcommon_pmu.c -+++ b/drivers/bcma/driver_chipcommon_pmu.c -@@ -56,6 +56,109 @@ void bcma_chipco_regctl_maskset(struct b - } - EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset); - -+static u32 bcma_pmu_xtalfreq(struct bcma_drv_cc *cc) -+{ -+ u32 ilp_ctl, alp_hz; -+ -+ if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) & -+ BCMA_CC_PMU_STAT_EXT_LPO_AVAIL)) -+ return 0; -+ -+ bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, -+ BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT)); -+ usleep_range(1000, 2000); -+ -+ ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ); -+ ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK; -+ -+ bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0); -+ -+ alp_hz = ilp_ctl * 32768 / 4; -+ return (alp_hz + 50000) / 100000 * 100; -+} -+ -+static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq) -+{ -+ struct bcma_bus *bus = cc->core->bus; -+ u32 freq_tgt_target = 0, freq_tgt_current; -+ u32 pll0, mask; -+ -+ switch (bus->chipinfo.id) { -+ case BCMA_CHIP_ID_BCM43142: -+ /* pmu2_xtaltab0_adfll_485 */ -+ switch (xtalfreq) { -+ case 12000: -+ freq_tgt_target = 0x50D52; -+ break; -+ case 20000: -+ freq_tgt_target = 0x307FE; -+ break; -+ case 26000: -+ freq_tgt_target = 0x254EA; -+ break; -+ case 37400: -+ freq_tgt_target = 0x19EF8; -+ break; -+ case 52000: -+ freq_tgt_target = 0x12A75; -+ break; -+ } -+ break; -+ } -+ -+ if (!freq_tgt_target) { -+ bcma_err(bus, "Unknown TGT frequency for xtalfreq %d\n", -+ xtalfreq); -+ return; -+ } -+ -+ pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0); -+ freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >> -+ BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT; -+ -+ if (freq_tgt_current == freq_tgt_target) { -+ bcma_debug(bus, "Target TGT frequency already set\n"); -+ return; -+ } -+ -+ /* Turn off PLL */ -+ switch (bus->chipinfo.id) { -+ case BCMA_CHIP_ID_BCM43142: -+ mask = (u32)~(BCMA_RES_4314_HT_AVAIL | -+ BCMA_RES_4314_MACPHY_CLK_AVAIL); -+ -+ bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask); -+ bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask); -+ bcma_wait_value(cc->core, BCMA_CLKCTLST, -+ BCMA_CLKCTLST_HAVEHT, 0, 20000); -+ break; -+ } -+ -+ pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK; -+ pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT; -+ bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0); -+ -+ /* Flush */ -+ if (cc->pmu.rev >= 2) -+ bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD); -+ -+ /* TODO: Do we need to update OTP? */ -+} -+ -+static void bcma_pmu_pll_init(struct bcma_drv_cc *cc) -+{ -+ struct bcma_bus *bus = cc->core->bus; -+ u32 xtalfreq = bcma_pmu_xtalfreq(cc); -+ -+ switch (bus->chipinfo.id) { -+ case BCMA_CHIP_ID_BCM43142: -+ if (xtalfreq == 0) -+ xtalfreq = 20000; -+ bcma_pmu2_pll_init0(cc, xtalfreq); -+ break; -+ } -+} -+ - static void bcma_pmu_resources_init(struct bcma_drv_cc *cc) - { - struct bcma_bus *bus = cc->core->bus; -@@ -66,6 +169,25 @@ static void bcma_pmu_resources_init(stru - min_msk = 0x200D; - max_msk = 0xFFFF; - break; -+ case BCMA_CHIP_ID_BCM43142: -+ min_msk = BCMA_RES_4314_LPLDO_PU | -+ BCMA_RES_4314_PMU_SLEEP_DIS | -+ BCMA_RES_4314_PMU_BG_PU | -+ BCMA_RES_4314_CBUCK_LPOM_PU | -+ BCMA_RES_4314_CBUCK_PFM_PU | -+ BCMA_RES_4314_CLDO_PU | -+ BCMA_RES_4314_LPLDO2_LVM | -+ BCMA_RES_4314_WL_PMU_PU | -+ BCMA_RES_4314_LDO3P3_PU | -+ BCMA_RES_4314_OTP_PU | -+ BCMA_RES_4314_WL_PWRSW_PU | -+ BCMA_RES_4314_LQ_AVAIL | -+ BCMA_RES_4314_LOGIC_RET | -+ BCMA_RES_4314_MEM_SLEEP | -+ BCMA_RES_4314_MACPHY_RET | -+ BCMA_RES_4314_WL_CORE_READY; -+ max_msk = 0x3FFFFFFF; -+ break; - default: - bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n", - bus->chipinfo.id); -@@ -165,6 +287,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c - bcma_cc_set32(cc, BCMA_CC_PMU_CTL, - BCMA_CC_PMU_CTL_NOILPONW); - -+ bcma_pmu_pll_init(cc); - bcma_pmu_resources_init(cc); - bcma_pmu_workarounds(cc); - } -@@ -480,6 +603,8 @@ void bcma_pmu_spuravoid_pllupdate(struct - tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW; - break; - -+ case BCMA_CHIP_ID_BCM43131: -+ case BCMA_CHIP_ID_BCM43217: - case BCMA_CHIP_ID_BCM43227: - case BCMA_CHIP_ID_BCM43228: - case BCMA_CHIP_ID_BCM43428: ---- a/drivers/bcma/driver_chipcommon_sflash.c -+++ b/drivers/bcma/driver_chipcommon_sflash.c -@@ -30,7 +30,7 @@ struct bcma_sflash_tbl_e { - u16 numblocks; - }; - --static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = { -+static const struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = { - { "M25P20", 0x11, 0x10000, 4, }, - { "M25P40", 0x12, 0x10000, 8, }, - -@@ -38,10 +38,10 @@ static struct bcma_sflash_tbl_e bcma_sfl - { "M25P32", 0x15, 0x10000, 64, }, - { "M25P64", 0x16, 0x10000, 128, }, - { "M25FL128", 0x17, 0x10000, 256, }, -- { 0 }, -+ { NULL }, - }; - --static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = { -+static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = { - { "SST25WF512", 1, 0x1000, 16, }, - { "SST25VF512", 0x48, 0x1000, 16, }, - { "SST25WF010", 2, 0x1000, 32, }, -@@ -56,10 +56,10 @@ static struct bcma_sflash_tbl_e bcma_sfl - { "SST25VF016", 0x41, 0x1000, 512, }, - { "SST25VF032", 0x4a, 0x1000, 1024, }, - { "SST25VF064", 0x4b, 0x1000, 2048, }, -- { 0 }, -+ { NULL }, - }; - --static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = { -+static const struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = { - { "AT45DB011", 0xc, 256, 512, }, - { "AT45DB021", 0x14, 256, 1024, }, - { "AT45DB041", 0x1c, 256, 2048, }, -@@ -67,7 +67,7 @@ static struct bcma_sflash_tbl_e bcma_sfl - { "AT45DB161", 0x2c, 512, 4096, }, - { "AT45DB321", 0x34, 512, 8192, }, - { "AT45DB642", 0x3c, 1024, 8192, }, -- { 0 }, -+ { NULL }, - }; - - static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode) -@@ -89,7 +89,7 @@ int bcma_sflash_init(struct bcma_drv_cc - { - struct bcma_bus *bus = cc->core->bus; - struct bcma_sflash *sflash = &cc->sflash; -- struct bcma_sflash_tbl_e *e; -+ const struct bcma_sflash_tbl_e *e; - u32 id, id2; - - switch (cc->capabilities & BCMA_CC_CAP_FLASHT) { ---- a/drivers/bcma/driver_gpio.c -+++ b/drivers/bcma/driver_gpio.c -@@ -9,6 +9,9 @@ - */ - - #include <linux/gpio.h> -+#include <linux/irq.h> -+#include <linux/interrupt.h> -+#include <linux/irqdomain.h> - #include <linux/export.h> - #include <linux/bcma/bcma.h> - -@@ -73,19 +76,136 @@ static void bcma_gpio_free(struct gpio_c - bcma_chipco_gpio_pullup(cc, 1 << gpio, 0); - } - -+#if IS_BUILTIN(CONFIG_BCMA_HOST_SOC) - static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) - { - struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); - - if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC) -- return bcma_core_irq(cc->core); -+ return irq_find_mapping(cc->irq_domain, gpio); - else - return -EINVAL; - } - -+static void bcma_gpio_irq_unmask(struct irq_data *d) -+{ -+ struct bcma_drv_cc *cc = irq_data_get_irq_chip_data(d); -+ int gpio = irqd_to_hwirq(d); -+ u32 val = bcma_chipco_gpio_in(cc, BIT(gpio)); -+ -+ bcma_chipco_gpio_polarity(cc, BIT(gpio), val); -+ bcma_chipco_gpio_intmask(cc, BIT(gpio), BIT(gpio)); -+} -+ -+static void bcma_gpio_irq_mask(struct irq_data *d) -+{ -+ struct bcma_drv_cc *cc = irq_data_get_irq_chip_data(d); -+ int gpio = irqd_to_hwirq(d); -+ -+ bcma_chipco_gpio_intmask(cc, BIT(gpio), 0); -+} -+ -+static struct irq_chip bcma_gpio_irq_chip = { -+ .name = "BCMA-GPIO", -+ .irq_mask = bcma_gpio_irq_mask, -+ .irq_unmask = bcma_gpio_irq_unmask, -+}; -+ -+static irqreturn_t bcma_gpio_irq_handler(int irq, void *dev_id) -+{ -+ struct bcma_drv_cc *cc = dev_id; -+ u32 val = bcma_cc_read32(cc, BCMA_CC_GPIOIN); -+ u32 mask = bcma_cc_read32(cc, BCMA_CC_GPIOIRQ); -+ u32 pol = bcma_cc_read32(cc, BCMA_CC_GPIOPOL); -+ unsigned long irqs = (val ^ pol) & mask; -+ int gpio; -+ -+ if (!irqs) -+ return IRQ_NONE; -+ -+ for_each_set_bit(gpio, &irqs, cc->gpio.ngpio) -+ generic_handle_irq(bcma_gpio_to_irq(&cc->gpio, gpio)); -+ bcma_chipco_gpio_polarity(cc, irqs, val & irqs); -+ -+ return IRQ_HANDLED; -+} -+ -+static int bcma_gpio_irq_domain_init(struct bcma_drv_cc *cc) -+{ -+ struct gpio_chip *chip = &cc->gpio; -+ int gpio, hwirq, err; -+ -+ if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC) -+ return 0; -+ -+ cc->irq_domain = irq_domain_add_linear(NULL, chip->ngpio, -+ &irq_domain_simple_ops, cc); -+ if (!cc->irq_domain) { -+ err = -ENODEV; -+ goto err_irq_domain; -+ } -+ for (gpio = 0; gpio < chip->ngpio; gpio++) { -+ int irq = irq_create_mapping(cc->irq_domain, gpio); -+ -+ irq_set_chip_data(irq, cc); -+ irq_set_chip_and_handler(irq, &bcma_gpio_irq_chip, -+ handle_simple_irq); -+ } -+ -+ hwirq = bcma_core_irq(cc->core); -+ err = request_irq(hwirq, bcma_gpio_irq_handler, IRQF_SHARED, "gpio", -+ cc); -+ if (err) -+ goto err_req_irq; -+ -+ bcma_chipco_gpio_intmask(cc, ~0, 0); -+ bcma_cc_set32(cc, BCMA_CC_IRQMASK, BCMA_CC_IRQ_GPIO); -+ -+ return 0; -+ -+err_req_irq: -+ for (gpio = 0; gpio < chip->ngpio; gpio++) { -+ int irq = irq_find_mapping(cc->irq_domain, gpio); -+ -+ irq_dispose_mapping(irq); -+ } -+ irq_domain_remove(cc->irq_domain); -+err_irq_domain: -+ return err; -+} -+ -+static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc) -+{ -+ struct gpio_chip *chip = &cc->gpio; -+ int gpio; -+ -+ if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC) -+ return; -+ -+ bcma_cc_mask32(cc, BCMA_CC_IRQMASK, ~BCMA_CC_IRQ_GPIO); -+ free_irq(bcma_core_irq(cc->core), cc); -+ for (gpio = 0; gpio < chip->ngpio; gpio++) { -+ int irq = irq_find_mapping(cc->irq_domain, gpio); -+ -+ irq_dispose_mapping(irq); -+ } -+ irq_domain_remove(cc->irq_domain); -+} -+#else -+static int bcma_gpio_irq_domain_init(struct bcma_drv_cc *cc) -+{ -+ return 0; -+} -+ -+static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc) -+{ -+} -+#endif -+ - int bcma_gpio_init(struct bcma_drv_cc *cc) - { - struct gpio_chip *chip = &cc->gpio; -+ int err; - - chip->label = "bcma_gpio"; - chip->owner = THIS_MODULE; -@@ -95,8 +215,18 @@ int bcma_gpio_init(struct bcma_drv_cc *c - chip->set = bcma_gpio_set_value; - chip->direction_input = bcma_gpio_direction_input; - chip->direction_output = bcma_gpio_direction_output; -+#if IS_BUILTIN(CONFIG_BCMA_HOST_SOC) - chip->to_irq = bcma_gpio_to_irq; -- chip->ngpio = 16; -+#endif -+ switch (cc->core->bus->chipinfo.id) { -+ case BCMA_CHIP_ID_BCM5357: -+ case BCMA_CHIP_ID_BCM53572: -+ chip->ngpio = 32; -+ break; -+ default: -+ chip->ngpio = 16; -+ } -+ - /* There is just one SoC in one device and its GPIO addresses should be - * deterministic to address them more easily. The other buses could get - * a random base number. */ -@@ -105,10 +235,21 @@ int bcma_gpio_init(struct bcma_drv_cc *c - else - chip->base = -1; - -- return gpiochip_add(chip); -+ err = bcma_gpio_irq_domain_init(cc); -+ if (err) -+ return err; -+ -+ err = gpiochip_add(chip); -+ if (err) { -+ bcma_gpio_irq_domain_exit(cc); -+ return err; -+ } -+ -+ return 0; - } - - int bcma_gpio_unregister(struct bcma_drv_cc *cc) - { -+ bcma_gpio_irq_domain_exit(cc); - return gpiochip_remove(&cc->gpio); - } ---- a/drivers/bcma/driver_pci.c -+++ b/drivers/bcma/driver_pci.c -@@ -31,7 +31,7 @@ static void bcma_pcie_write(struct bcma_ - pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data); - } - --static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy) -+static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u16 phy) - { - u32 v; - int i; -@@ -55,7 +55,7 @@ static void bcma_pcie_mdio_set_phy(struc - } - } - --static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address) -+static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u16 device, u8 address) - { - int max_retries = 10; - u16 ret = 0; -@@ -98,7 +98,7 @@ static u16 bcma_pcie_mdio_read(struct bc - return ret; - } - --static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device, -+static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u16 device, - u8 address, u16 data) - { - int max_retries = 10; -@@ -137,6 +137,13 @@ static void bcma_pcie_mdio_write(struct - pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0); - } - -+static u16 bcma_pcie_mdio_writeread(struct bcma_drv_pci *pc, u16 device, -+ u8 address, u16 data) -+{ -+ bcma_pcie_mdio_write(pc, device, address, data); -+ return bcma_pcie_mdio_read(pc, device, address); -+} -+ - /************************************************** - * Workarounds. - **************************************************/ -@@ -229,6 +236,32 @@ void bcma_core_pci_init(struct bcma_drv_ - bcma_core_pci_clientmode_init(pc); - } - -+void bcma_core_pci_power_save(struct bcma_bus *bus, bool up) -+{ -+ struct bcma_drv_pci *pc; -+ u16 data; -+ -+ if (bus->hosttype != BCMA_HOSTTYPE_PCI) -+ return; -+ -+ pc = &bus->drv_pci[0]; -+ -+ if (pc->core->id.rev >= 15 && pc->core->id.rev <= 20) { -+ data = up ? 0x74 : 0x7C; -+ bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1, -+ BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7F64); -+ bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1, -+ BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data); -+ } else if (pc->core->id.rev >= 21 && pc->core->id.rev <= 22) { -+ data = up ? 0x75 : 0x7D; -+ bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1, -+ BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7E65); -+ bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1, -+ BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data); -+ } -+} -+EXPORT_SYMBOL_GPL(bcma_core_pci_power_save); -+ - int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core, - bool enable) - { -@@ -262,7 +295,7 @@ out: - } - EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl); - --void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend) -+static void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend) - { - u32 w; - -@@ -274,4 +307,29 @@ void bcma_core_pci_extend_L1timer(struct - bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w); - bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG); - } --EXPORT_SYMBOL_GPL(bcma_core_pci_extend_L1timer); -+ -+void bcma_core_pci_up(struct bcma_bus *bus) -+{ -+ struct bcma_drv_pci *pc; -+ -+ if (bus->hosttype != BCMA_HOSTTYPE_PCI) -+ return; -+ -+ pc = &bus->drv_pci[0]; -+ -+ bcma_core_pci_extend_L1timer(pc, true); -+} -+EXPORT_SYMBOL_GPL(bcma_core_pci_up); -+ -+void bcma_core_pci_down(struct bcma_bus *bus) -+{ -+ struct bcma_drv_pci *pc; -+ -+ if (bus->hosttype != BCMA_HOSTTYPE_PCI) -+ return; -+ -+ pc = &bus->drv_pci[0]; -+ -+ bcma_core_pci_extend_L1timer(pc, false); -+} -+EXPORT_SYMBOL_GPL(bcma_core_pci_down); ---- a/drivers/bcma/driver_pci_host.c -+++ b/drivers/bcma/driver_pci_host.c -@@ -581,6 +581,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI - int bcma_core_pci_plat_dev_init(struct pci_dev *dev) - { - struct bcma_drv_pci_host *pc_host; -+ int readrq; - - if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) { - /* This is not a device on the PCI-core bridge. */ -@@ -595,6 +596,11 @@ int bcma_core_pci_plat_dev_init(struct p - dev->irq = bcma_core_irq(pc_host->pdev->core); - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); - -+ readrq = pcie_get_readrq(dev); -+ if (readrq > 128) { -+ pr_info("change PCIe max read request size from %i to 128\n", readrq); -+ pcie_set_readrq(dev, 128); -+ } - return 0; - } - EXPORT_SYMBOL(bcma_core_pci_plat_dev_init); ---- /dev/null -+++ b/drivers/bcma/driver_pcie2.c -@@ -0,0 +1,175 @@ -+/* -+ * Broadcom specific AMBA -+ * PCIe Gen 2 Core -+ * -+ * Copyright 2014, Broadcom Corporation -+ * Copyright 2014, Rafał Miłecki <zajec5@gmail.com> -+ * -+ * Licensed under the GNU/GPL. See COPYING for details. -+ */ -+ -+#include "bcma_private.h" -+#include <linux/bcma/bcma.h> -+ -+/************************************************** -+ * R/W ops. -+ **************************************************/ -+ -+#if 0 -+static u32 bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2 *pcie2, u32 addr) -+{ -+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr); -+ pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR); -+ return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA); -+} -+#endif -+ -+static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2 *pcie2, u32 addr, -+ u32 val) -+{ -+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr); -+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val); -+} -+ -+/************************************************** -+ * Init. -+ **************************************************/ -+ -+static u32 bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2 *pcie2, -+ bool enable) -+{ -+ u32 val; -+ -+ /* restore back to default */ -+ val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL); -+ val |= PCIE2_CLKC_DLYPERST; -+ val &= ~PCIE2_CLKC_DISSPROMLD; -+ if (enable) { -+ val &= ~PCIE2_CLKC_DLYPERST; -+ val |= PCIE2_CLKC_DISSPROMLD; -+ } -+ pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val); -+ /* flush */ -+ return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL); -+} -+ -+static void bcma_core_pcie2_set_ltr_vals(struct bcma_drv_pcie2 *pcie2) -+{ -+ /* LTR0 */ -+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844); -+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c); -+ /* LTR1 */ -+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848); -+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864); -+ /* LTR2 */ -+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C); -+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003); -+} -+ -+static void bcma_core_pcie2_hw_ltr_war(struct bcma_drv_pcie2 *pcie2) -+{ -+ u8 core_rev = pcie2->core->id.rev; -+ u32 devstsctr2; -+ -+ if (core_rev < 2 || core_rev == 10 || core_rev > 13) -+ return; -+ -+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, -+ PCIE2_CAP_DEVSTSCTRL2_OFFSET); -+ devstsctr2 = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA); -+ if (devstsctr2 & PCIE2_CAP_DEVSTSCTRL2_LTRENAB) { -+ /* force the right LTR values */ -+ bcma_core_pcie2_set_ltr_vals(pcie2); -+ -+ /* TODO: -+ si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0); */ -+ -+ /* enable the LTR */ -+ devstsctr2 |= PCIE2_CAP_DEVSTSCTRL2_LTRENAB; -+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, -+ PCIE2_CAP_DEVSTSCTRL2_OFFSET); -+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, devstsctr2); -+ -+ /* set the LTR state to be active */ -+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE, -+ PCIE2_LTR_ACTIVE); -+ usleep_range(1000, 2000); -+ -+ /* set the LTR state to be sleep */ -+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE, -+ PCIE2_LTR_SLEEP); -+ usleep_range(1000, 2000); -+ } -+} -+ -+static void pciedev_crwlpciegen2(struct bcma_drv_pcie2 *pcie2) -+{ -+ u8 core_rev = pcie2->core->id.rev; -+ bool pciewar160, pciewar162; -+ -+ pciewar160 = core_rev == 7 || core_rev == 9 || core_rev == 11; -+ pciewar162 = core_rev == 5 || core_rev == 7 || core_rev == 8 || -+ core_rev == 9 || core_rev == 11; -+ -+ if (!pciewar160 && !pciewar162) -+ return; -+ -+/* TODO */ -+#if 0 -+ pcie2_set32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL, -+ PCIE_DISABLE_L1CLK_GATING); -+#if 0 -+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, -+ PCIEGEN2_COE_PVT_TL_CTRL_0); -+ pcie2_mask32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, -+ ~(1 << COE_PVT_TL_CTRL_0_PM_DIS_L1_REENTRY_BIT)); -+#endif -+#endif -+} -+ -+static void pciedev_crwlpciegen2_180(struct bcma_drv_pcie2 *pcie2) -+{ -+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_PMCR_REFUP); -+ pcie2_set32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x1f); -+} -+ -+static void pciedev_crwlpciegen2_182(struct bcma_drv_pcie2 *pcie2) -+{ -+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_SBMBX); -+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 1 << 0); -+} -+ -+static void pciedev_reg_pm_clk_period(struct bcma_drv_pcie2 *pcie2) -+{ -+ struct bcma_drv_cc *drv_cc = &pcie2->core->bus->drv_cc; -+ u8 core_rev = pcie2->core->id.rev; -+ u32 alp_khz, pm_value; -+ -+ if (core_rev <= 13) { -+ alp_khz = bcma_pmu_get_alp_clock(drv_cc) / 1000; -+ pm_value = (1000000 * 2) / alp_khz; -+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, -+ PCIE2_PVT_REG_PM_CLK_PERIOD); -+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, pm_value); -+ } -+} -+ -+void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2) -+{ -+ struct bcma_chipinfo *ci = &pcie2->core->bus->chipinfo; -+ u32 tmp; -+ -+ tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54)); -+ if ((tmp & 0xe) >> 1 == 2) -+ bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17); -+ -+ /* TODO: Do we need pcie_reqsize? */ -+ -+ if (ci->id == BCMA_CHIP_ID_BCM4360 && ci->rev > 3) -+ bcma_core_pcie2_war_delay_perst_enab(pcie2, true); -+ bcma_core_pcie2_hw_ltr_war(pcie2); -+ pciedev_crwlpciegen2(pcie2); -+ pciedev_reg_pm_clk_period(pcie2); -+ pciedev_crwlpciegen2_180(pcie2); -+ pciedev_crwlpciegen2_182(pcie2); -+} ---- a/drivers/bcma/host_pci.c -+++ b/drivers/bcma/host_pci.c -@@ -188,8 +188,11 @@ static int bcma_host_pci_probe(struct pc - pci_write_config_dword(dev, 0x40, val & 0xffff00ff); - - /* SSB needed additional powering up, do we have any AMBA PCI cards? */ -- if (!pci_is_pcie(dev)) -- bcma_err(bus, "PCI card detected, report problems.\n"); -+ if (!pci_is_pcie(dev)) { -+ bcma_err(bus, "PCI card detected, they are not supported.\n"); -+ err = -ENXIO; -+ goto err_pci_release_regions; -+ } - - /* Map MMIO */ - err = -ENOMEM; -@@ -235,7 +238,6 @@ static void bcma_host_pci_remove(struct - pci_release_regions(dev); - pci_disable_device(dev); - kfree(bus); -- pci_set_drvdata(dev, NULL); - } - - #ifdef CONFIG_PM_SLEEP -@@ -267,14 +269,18 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc - - #endif /* CONFIG_PM_SLEEP */ - --static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = { -+static const struct pci_device_id bcma_pci_bridge_tbl[] = { - { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) }, -+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4313) }, - { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) }, - { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) }, - { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) }, - { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) }, - { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) }, - { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) }, -+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) }, -+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) }, -+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) }, - { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) }, - { 0, }, - }; ---- a/drivers/bcma/main.c -+++ b/drivers/bcma/main.c -@@ -69,28 +69,36 @@ static u16 bcma_cc_core_id(struct bcma_b - return BCMA_CORE_CHIPCOMMON; - } - --struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid) -+struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid, -+ u8 unit) - { - struct bcma_device *core; - - list_for_each_entry(core, &bus->cores, list) { -- if (core->id.id == coreid) -+ if (core->id.id == coreid && core->core_unit == unit) - return core; - } - return NULL; - } --EXPORT_SYMBOL_GPL(bcma_find_core); -+EXPORT_SYMBOL_GPL(bcma_find_core_unit); - --struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid, -- u8 unit) -+bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value, -+ int timeout) - { -- struct bcma_device *core; -+ unsigned long deadline = jiffies + timeout; -+ u32 val; - -- list_for_each_entry(core, &bus->cores, list) { -- if (core->id.id == coreid && core->core_unit == unit) -- return core; -- } -- return NULL; -+ do { -+ val = bcma_read32(core, reg); -+ if ((val & mask) == value) -+ return true; -+ cpu_relax(); -+ udelay(10); -+ } while (!time_after_eq(jiffies, deadline)); -+ -+ bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg); -+ -+ return false; - } - - static void bcma_release_core_dev(struct device *dev) -@@ -115,6 +123,7 @@ static int bcma_register_cores(struct bc - case BCMA_CORE_CHIPCOMMON: - case BCMA_CORE_PCI: - case BCMA_CORE_PCIE: -+ case BCMA_CORE_PCIE2: - case BCMA_CORE_MIPS_74K: - case BCMA_CORE_4706_MAC_GBIT_COMMON: - continue; -@@ -148,6 +157,7 @@ static int bcma_register_cores(struct bc - bcma_err(bus, - "Could not register dev for core 0x%03X\n", - core->id.id); -+ put_device(&core->dev); - continue; - } - core->dev_registered = true; -@@ -218,7 +228,7 @@ int bcma_bus_register(struct bcma_bus *b - err = bcma_bus_scan(bus); - if (err) { - bcma_err(bus, "Failed to scan: %d\n", err); -- return -1; -+ return err; - } - - /* Early init CC core */ -@@ -263,6 +273,13 @@ int bcma_bus_register(struct bcma_bus *b - bcma_core_pci_init(&bus->drv_pci[1]); - } - -+ /* Init PCIe Gen 2 core */ -+ core = bcma_find_core_unit(bus, BCMA_CORE_PCIE2, 0); -+ if (core) { -+ bus->drv_pcie2.core = core; -+ bcma_core_pcie2_init(&bus->drv_pcie2); -+ } -+ - /* Init GBIT MAC COMMON core */ - core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON); - if (core) { ---- a/drivers/bcma/scan.c -+++ b/drivers/bcma/scan.c -@@ -32,6 +32,18 @@ static const struct bcma_device_id_name - { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" }, - { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" }, - { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" }, -+ { BCMA_CORE_NS_PCIEG2, "PCIe Gen 2" }, -+ { BCMA_CORE_NS_DMA, "DMA" }, -+ { BCMA_CORE_NS_SDIO3, "SDIO3" }, -+ { BCMA_CORE_NS_USB20, "USB 2.0" }, -+ { BCMA_CORE_NS_USB30, "USB 3.0" }, -+ { BCMA_CORE_NS_A9JTAG, "ARM Cortex A9 JTAG" }, -+ { BCMA_CORE_NS_DDR23, "Denali DDR2/DDR3 memory controller" }, -+ { BCMA_CORE_NS_ROM, "ROM" }, -+ { BCMA_CORE_NS_NAND, "NAND flash controller" }, -+ { BCMA_CORE_NS_QSPI, "SPI flash controller" }, -+ { BCMA_CORE_NS_CHIPCOMMON_B, "Chipcommon B" }, -+ { BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" }, - { BCMA_CORE_AMEMC, "AMEMC (DDR)" }, - { BCMA_CORE_ALTA, "ALTA (I2S)" }, - { BCMA_CORE_INVALID, "Invalid" }, -@@ -201,7 +213,7 @@ static s32 bcma_erom_get_mst_port(struct - return ent; - } - --static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr, -+static u32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr, - u32 type, u8 port) - { - u32 addrl, addrh, sizel, sizeh = 0; -@@ -213,7 +225,7 @@ static s32 bcma_erom_get_addr_desc(struc - ((ent & SCAN_ADDR_TYPE) != type) || - (((ent & SCAN_ADDR_PORT) >> SCAN_ADDR_PORT_SHIFT) != port)) { - bcma_erom_push_ent(eromptr); -- return -EINVAL; -+ return (u32)-EINVAL; - } - - addrl = ent & SCAN_ADDR_ADDR; -@@ -257,11 +269,13 @@ static struct bcma_device *bcma_find_cor - return NULL; - } - -+#define IS_ERR_VALUE_U32(x) ((x) >= (u32)-MAX_ERRNO) -+ - static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr, - struct bcma_device_id *match, int core_num, - struct bcma_device *core) - { -- s32 tmp; -+ u32 tmp; - u8 i, j; - s32 cia, cib; - u8 ports[2], wrappers[2]; -@@ -339,11 +353,11 @@ static int bcma_get_next_core(struct bcm - * the main register space for the core - */ - tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0); -- if (tmp <= 0) { -+ if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) { - /* Try again to see if it is a bridge */ - tmp = bcma_erom_get_addr_desc(bus, eromptr, - SCAN_ADDR_TYPE_BRIDGE, 0); -- if (tmp <= 0) { -+ if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) { - return -EILSEQ; - } else { - bcma_info(bus, "Bridge found\n"); -@@ -357,7 +371,7 @@ static int bcma_get_next_core(struct bcm - for (j = 0; ; j++) { - tmp = bcma_erom_get_addr_desc(bus, eromptr, - SCAN_ADDR_TYPE_SLAVE, i); -- if (tmp < 0) { -+ if (IS_ERR_VALUE_U32(tmp)) { - /* no more entries for port _i_ */ - /* pr_debug("erom: slave port %d " - * "has %d descriptors\n", i, j); */ -@@ -374,7 +388,7 @@ static int bcma_get_next_core(struct bcm - for (j = 0; ; j++) { - tmp = bcma_erom_get_addr_desc(bus, eromptr, - SCAN_ADDR_TYPE_MWRAP, i); -- if (tmp < 0) { -+ if (IS_ERR_VALUE_U32(tmp)) { - /* no more entries for port _i_ */ - /* pr_debug("erom: master wrapper %d " - * "has %d descriptors\n", i, j); */ -@@ -392,7 +406,7 @@ static int bcma_get_next_core(struct bcm - for (j = 0; ; j++) { - tmp = bcma_erom_get_addr_desc(bus, eromptr, - SCAN_ADDR_TYPE_SWRAP, i + hack); -- if (tmp < 0) { -+ if (IS_ERR_VALUE_U32(tmp)) { - /* no more entries for port _i_ */ - /* pr_debug("erom: master wrapper %d " - * has %d descriptors\n", i, j); */ ---- a/drivers/bcma/sprom.c -+++ b/drivers/bcma/sprom.c -@@ -72,12 +72,12 @@ fail: - * R/W ops. - **************************************************/ - --static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom) -+static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom, -+ size_t words) - { - int i; -- for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++) -- sprom[i] = bcma_read16(bus->drv_cc.core, -- offset + (i * 2)); -+ for (i = 0; i < words; i++) -+ sprom[i] = bcma_read16(bus->drv_cc.core, offset + (i * 2)); - } - - /************************************************** -@@ -124,29 +124,29 @@ static inline u8 bcma_crc8(u8 crc, u8 da - return t[crc ^ data]; - } - --static u8 bcma_sprom_crc(const u16 *sprom) -+static u8 bcma_sprom_crc(const u16 *sprom, size_t words) - { - int word; - u8 crc = 0xFF; - -- for (word = 0; word < SSB_SPROMSIZE_WORDS_R4 - 1; word++) { -+ for (word = 0; word < words - 1; word++) { - crc = bcma_crc8(crc, sprom[word] & 0x00FF); - crc = bcma_crc8(crc, (sprom[word] & 0xFF00) >> 8); - } -- crc = bcma_crc8(crc, sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & 0x00FF); -+ crc = bcma_crc8(crc, sprom[words - 1] & 0x00FF); - crc ^= 0xFF; - - return crc; - } - --static int bcma_sprom_check_crc(const u16 *sprom) -+static int bcma_sprom_check_crc(const u16 *sprom, size_t words) - { - u8 crc; - u8 expected_crc; - u16 tmp; - -- crc = bcma_sprom_crc(sprom); -- tmp = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_CRC; -+ crc = bcma_sprom_crc(sprom, words); -+ tmp = sprom[words - 1] & SSB_SPROM_REVISION_CRC; - expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT; - if (crc != expected_crc) - return -EPROTO; -@@ -154,21 +154,25 @@ static int bcma_sprom_check_crc(const u1 - return 0; - } - --static int bcma_sprom_valid(const u16 *sprom) -+static int bcma_sprom_valid(struct bcma_bus *bus, const u16 *sprom, -+ size_t words) - { - u16 revision; - int err; - -- err = bcma_sprom_check_crc(sprom); -+ err = bcma_sprom_check_crc(sprom, words); - if (err) - return err; - -- revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV; -- if (revision != 8 && revision != 9) { -+ revision = sprom[words - 1] & SSB_SPROM_REVISION_REV; -+ if (revision != 8 && revision != 9 && revision != 10) { - pr_err("Unsupported SPROM revision: %d\n", revision); - return -ENOENT; - } - -+ bus->sprom.revision = revision; -+ bcma_debug(bus, "Found SPROM revision %d\n", revision); -+ - return 0; - } - -@@ -197,6 +201,23 @@ static int bcma_sprom_valid(const u16 *s - SPEX(_field[7], _offset + 14, _mask, _shift); \ - } while (0) - -+static s8 sprom_extract_antgain(const u16 *in, u16 offset, u16 mask, u16 shift) -+{ -+ u16 v; -+ u8 gain; -+ -+ v = in[SPOFF(offset)]; -+ gain = (v & mask) >> shift; -+ if (gain == 0xFF) { -+ gain = 8; /* If unset use 2dBm */ -+ } else { -+ /* Q5.2 Fractional part is stored in 0xC0 */ -+ gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2); -+ } -+ -+ return (s8)gain; -+} -+ - static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom) - { - u16 v, o; -@@ -208,9 +229,6 @@ static void bcma_sprom_extract_r8(struct - BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) != - ARRAY_SIZE(bus->sprom.core_pwr_info)); - -- bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & -- SSB_SPROM_REVISION_REV; -- - for (i = 0; i < 3; i++) { - v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i]; - *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v); -@@ -380,14 +398,22 @@ static void bcma_sprom_extract_r8(struct - SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0); - - /* Extract the antenna gain values. */ -- SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01, -- SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT); -- SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01, -- SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT); -- SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23, -- SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT); -- SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23, -- SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT); -+ bus->sprom.antenna_gain.a0 = sprom_extract_antgain(sprom, -+ SSB_SPROM8_AGAIN01, -+ SSB_SPROM8_AGAIN0, -+ SSB_SPROM8_AGAIN0_SHIFT); -+ bus->sprom.antenna_gain.a1 = sprom_extract_antgain(sprom, -+ SSB_SPROM8_AGAIN01, -+ SSB_SPROM8_AGAIN1, -+ SSB_SPROM8_AGAIN1_SHIFT); -+ bus->sprom.antenna_gain.a2 = sprom_extract_antgain(sprom, -+ SSB_SPROM8_AGAIN23, -+ SSB_SPROM8_AGAIN2, -+ SSB_SPROM8_AGAIN2_SHIFT); -+ bus->sprom.antenna_gain.a3 = sprom_extract_antgain(sprom, -+ SSB_SPROM8_AGAIN23, -+ SSB_SPROM8_AGAIN3, -+ SSB_SPROM8_AGAIN3_SHIFT); - - SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON, - SSB_SPROM8_LEDDC_ON_SHIFT); -@@ -502,12 +528,14 @@ static bool bcma_sprom_onchip_available( - case BCMA_CHIP_ID_BCM4331: - present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT; - break; -- -+ case BCMA_CHIP_ID_BCM43142: - case BCMA_CHIP_ID_BCM43224: - case BCMA_CHIP_ID_BCM43225: - /* for these chips OTP is always available */ - present = true; - break; -+ case BCMA_CHIP_ID_BCM43131: -+ case BCMA_CHIP_ID_BCM43217: - case BCMA_CHIP_ID_BCM43227: - case BCMA_CHIP_ID_BCM43228: - case BCMA_CHIP_ID_BCM43428: -@@ -550,7 +578,9 @@ int bcma_sprom_get(struct bcma_bus *bus) - { - u16 offset = BCMA_CC_SPROM; - u16 *sprom; -- int err = 0; -+ size_t sprom_sizes[] = { SSB_SPROMSIZE_WORDS_R4, -+ SSB_SPROMSIZE_WORDS_R10, }; -+ int i, err = 0; - - if (!bus->drv_cc.core) - return -EOPNOTSUPP; -@@ -579,32 +609,37 @@ int bcma_sprom_get(struct bcma_bus *bus) - } - } - -- sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16), -- GFP_KERNEL); -- if (!sprom) -- return -ENOMEM; -- - if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 || - bus->chipinfo.id == BCMA_CHIP_ID_BCM43431) - bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false); - - bcma_debug(bus, "SPROM offset 0x%x\n", offset); -- bcma_sprom_read(bus, offset, sprom); -+ for (i = 0; i < ARRAY_SIZE(sprom_sizes); i++) { -+ size_t words = sprom_sizes[i]; -+ -+ sprom = kcalloc(words, sizeof(u16), GFP_KERNEL); -+ if (!sprom) -+ return -ENOMEM; -+ -+ bcma_sprom_read(bus, offset, sprom, words); -+ err = bcma_sprom_valid(bus, sprom, words); -+ if (!err) -+ break; -+ -+ kfree(sprom); -+ } - - if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 || - bus->chipinfo.id == BCMA_CHIP_ID_BCM43431) - bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true); - -- err = bcma_sprom_valid(sprom); - if (err) { -- bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n"); -+ bcma_warn(bus, "Invalid SPROM read from the PCIe card, trying to use fallback SPROM\n"); - err = bcma_fill_sprom_with_fallback(bus, &bus->sprom); -- goto out; -+ } else { -+ bcma_sprom_extract_r8(bus, sprom); -+ kfree(sprom); - } - -- bcma_sprom_extract_r8(bus, sprom); -- --out: -- kfree(sprom); - return err; - } ---- a/include/linux/bcma/bcma.h -+++ b/include/linux/bcma/bcma.h -@@ -6,6 +6,7 @@ - - #include <linux/bcma/bcma_driver_chipcommon.h> - #include <linux/bcma/bcma_driver_pci.h> -+#include <linux/bcma/bcma_driver_pcie2.h> - #include <linux/bcma/bcma_driver_mips.h> - #include <linux/bcma/bcma_driver_gmac_cmn.h> - #include <linux/ssb/ssb.h> /* SPROM sharing */ -@@ -72,7 +73,19 @@ struct bcma_host_ops { - /* Core-ID values. */ - #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */ - #define BCMA_CORE_4706_CHIPCOMMON 0x500 -+#define BCMA_CORE_NS_PCIEG2 0x501 -+#define BCMA_CORE_NS_DMA 0x502 -+#define BCMA_CORE_NS_SDIO3 0x503 -+#define BCMA_CORE_NS_USB20 0x504 -+#define BCMA_CORE_NS_USB30 0x505 -+#define BCMA_CORE_NS_A9JTAG 0x506 -+#define BCMA_CORE_NS_DDR23 0x507 -+#define BCMA_CORE_NS_ROM 0x508 -+#define BCMA_CORE_NS_NAND 0x509 -+#define BCMA_CORE_NS_QSPI 0x50A -+#define BCMA_CORE_NS_CHIPCOMMON_B 0x50B - #define BCMA_CORE_4706_SOC_RAM 0x50E -+#define BCMA_CORE_ARMCA9 0x510 - #define BCMA_CORE_4706_MAC_GBIT 0x52D - #define BCMA_CORE_AMEMC 0x52E /* DDR1/2 memory controller core */ - #define BCMA_CORE_ALTA 0x534 /* I2S core */ -@@ -144,6 +157,10 @@ struct bcma_host_ops { - - /* Chip IDs of PCIe devices */ - #define BCMA_CHIP_ID_BCM4313 0x4313 -+#define BCMA_CHIP_ID_BCM43142 43142 -+#define BCMA_CHIP_ID_BCM43131 43131 -+#define BCMA_CHIP_ID_BCM43217 43217 -+#define BCMA_CHIP_ID_BCM43222 43222 - #define BCMA_CHIP_ID_BCM43224 43224 - #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8 - #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa -@@ -176,6 +193,11 @@ struct bcma_host_ops { - #define BCMA_PKG_ID_BCM5357 11 - #define BCMA_CHIP_ID_BCM53572 53572 - #define BCMA_PKG_ID_BCM47188 9 -+#define BCMA_CHIP_ID_BCM4707 53010 -+#define BCMA_PKG_ID_BCM4707 1 -+#define BCMA_PKG_ID_BCM4708 2 -+#define BCMA_PKG_ID_BCM4709 0 -+#define BCMA_CHIP_ID_BCM53018 53018 - - /* Board types (on PCI usually equals to the subsystem dev id) */ - /* BCM4313 */ -@@ -315,6 +337,7 @@ struct bcma_bus { - - struct bcma_drv_cc drv_cc; - struct bcma_drv_pci drv_pci[2]; -+ struct bcma_drv_pcie2 drv_pcie2; - struct bcma_drv_mips drv_mips; - struct bcma_drv_gmac_cmn drv_gmac_cmn; - -@@ -400,7 +423,14 @@ static inline void bcma_maskset16(struct - bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set); - } - --extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid); -+extern struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid, -+ u8 unit); -+static inline struct bcma_device *bcma_find_core(struct bcma_bus *bus, -+ u16 coreid) -+{ -+ return bcma_find_core_unit(bus, coreid, 0); -+} -+ - extern bool bcma_core_is_enabled(struct bcma_device *core); - extern void bcma_core_disable(struct bcma_device *core, u32 flags); - extern int bcma_core_enable(struct bcma_device *core, u32 flags); ---- a/include/linux/bcma/bcma_driver_chipcommon.h -+++ b/include/linux/bcma/bcma_driver_chipcommon.h -@@ -330,6 +330,8 @@ - #define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */ - #define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */ - #define BCMA_CC_PMU_STAT 0x0608 /* PMU status */ -+#define BCMA_CC_PMU_STAT_EXT_LPO_AVAIL 0x00000100 -+#define BCMA_CC_PMU_STAT_WDRESET 0x00000080 - #define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */ - #define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */ - #define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */ -@@ -355,6 +357,11 @@ - #define BCMA_CC_REGCTL_DATA 0x065C - #define BCMA_CC_PLLCTL_ADDR 0x0660 - #define BCMA_CC_PLLCTL_DATA 0x0664 -+#define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */ -+#define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */ -+#define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF -+#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK 0x80000000 -+#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT 31 - #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */ - /* NAND flash MLC controller registers (corerev >= 38) */ - #define BCMA_CC_NAND_REVISION 0x0C00 -@@ -435,6 +442,23 @@ - #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007 - #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0 - -+/* PMU rev 15 */ -+#define BCMA_CC_PMU15_PLL_PLLCTL0 0 -+#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK 0x00000003 -+#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT 0 -+#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC -+#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT 2 -+#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000 -+#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT 22 -+#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK 0x07000000 -+#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT 24 -+#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000 -+#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT 27 -+#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK 0x40000000 -+#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT 30 -+#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000 -+#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT 31 -+ - /* ALP clock on pre-PMU chips */ - #define BCMA_CC_PMU_ALP_CLOCK 20000000 - /* HT clock for systems with PMU-enabled chipcommon */ -@@ -507,6 +531,37 @@ - #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18) - #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19) - -+#define BCMA_RES_4314_LPLDO_PU BIT(0) -+#define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1) -+#define BCMA_RES_4314_PMU_BG_PU BIT(2) -+#define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3) -+#define BCMA_RES_4314_CBUCK_PFM_PU BIT(4) -+#define BCMA_RES_4314_CLDO_PU BIT(5) -+#define BCMA_RES_4314_LPLDO2_LVM BIT(6) -+#define BCMA_RES_4314_WL_PMU_PU BIT(7) -+#define BCMA_RES_4314_LNLDO_PU BIT(8) -+#define BCMA_RES_4314_LDO3P3_PU BIT(9) -+#define BCMA_RES_4314_OTP_PU BIT(10) -+#define BCMA_RES_4314_XTAL_PU BIT(11) -+#define BCMA_RES_4314_WL_PWRSW_PU BIT(12) -+#define BCMA_RES_4314_LQ_AVAIL BIT(13) -+#define BCMA_RES_4314_LOGIC_RET BIT(14) -+#define BCMA_RES_4314_MEM_SLEEP BIT(15) -+#define BCMA_RES_4314_MACPHY_RET BIT(16) -+#define BCMA_RES_4314_WL_CORE_READY BIT(17) -+#define BCMA_RES_4314_ILP_REQ BIT(18) -+#define BCMA_RES_4314_ALP_AVAIL BIT(19) -+#define BCMA_RES_4314_MISC_PWRSW_PU BIT(20) -+#define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21) -+#define BCMA_RES_4314_RX_PWRSW_PU BIT(22) -+#define BCMA_RES_4314_RADIO_PU BIT(23) -+#define BCMA_RES_4314_VCO_LDO_PU BIT(24) -+#define BCMA_RES_4314_AFE_LDO_PU BIT(25) -+#define BCMA_RES_4314_RX_LDO_PU BIT(26) -+#define BCMA_RES_4314_TX_LDO_PU BIT(27) -+#define BCMA_RES_4314_HT_AVAIL BIT(28) -+#define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29) -+ - /* Data for the PMU, if available. - * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU) - */ -@@ -585,6 +640,7 @@ struct bcma_drv_cc { - spinlock_t gpio_lock; - #ifdef CONFIG_BCMA_DRIVER_GPIO - struct gpio_chip gpio; -+ struct irq_domain *irq_domain; - #endif - }; - ---- a/include/linux/bcma/bcma_driver_pci.h -+++ b/include/linux/bcma/bcma_driver_pci.h -@@ -181,10 +181,31 @@ struct pci_dev; - - #define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8 - -+#define BCMA_CORE_PCI_ -+ -+/* MDIO devices (SERDES modules) */ -+#define BCMA_CORE_PCI_MDIO_IEEE0 0x000 -+#define BCMA_CORE_PCI_MDIO_IEEE1 0x001 -+#define BCMA_CORE_PCI_MDIO_BLK0 0x800 -+#define BCMA_CORE_PCI_MDIO_BLK1 0x801 -+#define BCMA_CORE_PCI_MDIO_BLK1_MGMT0 0x16 -+#define BCMA_CORE_PCI_MDIO_BLK1_MGMT1 0x17 -+#define BCMA_CORE_PCI_MDIO_BLK1_MGMT2 0x18 -+#define BCMA_CORE_PCI_MDIO_BLK1_MGMT3 0x19 -+#define BCMA_CORE_PCI_MDIO_BLK1_MGMT4 0x1A -+#define BCMA_CORE_PCI_MDIO_BLK2 0x802 -+#define BCMA_CORE_PCI_MDIO_BLK3 0x803 -+#define BCMA_CORE_PCI_MDIO_BLK4 0x804 -+#define BCMA_CORE_PCI_MDIO_TXPLL 0x808 /* TXPLL register block idx */ -+#define BCMA_CORE_PCI_MDIO_TXCTRL0 0x820 -+#define BCMA_CORE_PCI_MDIO_SERDESID 0x831 -+#define BCMA_CORE_PCI_MDIO_RXCTRL0 0x840 -+ - /* PCIE Root Capability Register bits (Host mode only) */ - #define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001 - - struct bcma_drv_pci; -+struct bcma_bus; - - #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE - struct bcma_drv_pci_host { -@@ -219,7 +240,9 @@ struct bcma_drv_pci { - extern void bcma_core_pci_init(struct bcma_drv_pci *pc); - extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, - struct bcma_device *core, bool enable); --extern void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend); -+extern void bcma_core_pci_up(struct bcma_bus *bus); -+extern void bcma_core_pci_down(struct bcma_bus *bus); -+extern void bcma_core_pci_power_save(struct bcma_bus *bus, bool up); - - extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev); - extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev); ---- /dev/null -+++ b/include/linux/bcma/bcma_driver_pcie2.h -@@ -0,0 +1,158 @@ -+#ifndef LINUX_BCMA_DRIVER_PCIE2_H_ -+#define LINUX_BCMA_DRIVER_PCIE2_H_ -+ -+#define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000 -+#define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */ -+#define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */ -+#define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */ -+#define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010 -+#define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */ -+#define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */ -+#define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */ -+#define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004 -+#define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008 -+#define BCMA_CORE_PCIE2_EP_PM_CONTROL 0x000C -+#define BCMA_CORE_PCIE2_EP_PM_STATUS 0x0010 -+#define BCMA_CORE_PCIE2_EP_LTR_CONTROL 0x0014 -+#define BCMA_CORE_PCIE2_EP_LTR_STATUS 0x0018 -+#define BCMA_CORE_PCIE2_EP_OBFF_STATUS 0x001C -+#define BCMA_CORE_PCIE2_PCIE_ERR_STATUS 0x0020 -+#define BCMA_CORE_PCIE2_RC_AXI_CONFIG 0x0100 -+#define BCMA_CORE_PCIE2_EP_AXI_CONFIG 0x0104 -+#define BCMA_CORE_PCIE2_RXDEBUG_STATUS0 0x0108 -+#define BCMA_CORE_PCIE2_RXDEBUG_CONTROL0 0x010C -+#define BCMA_CORE_PCIE2_CONFIGINDADDR 0x0120 -+#define BCMA_CORE_PCIE2_CONFIGINDDATA 0x0124 -+#define BCMA_CORE_PCIE2_MDIOCONTROL 0x0128 -+#define BCMA_CORE_PCIE2_MDIOWRDATA 0x012C -+#define BCMA_CORE_PCIE2_MDIORDDATA 0x0130 -+#define BCMA_CORE_PCIE2_DATAINTF 0x0180 -+#define BCMA_CORE_PCIE2_D2H_INTRLAZY_0 0x0188 -+#define BCMA_CORE_PCIE2_H2D_INTRLAZY_0 0x018c -+#define BCMA_CORE_PCIE2_H2D_INTSTAT_0 0x0190 -+#define BCMA_CORE_PCIE2_H2D_INTMASK_0 0x0194 -+#define BCMA_CORE_PCIE2_D2H_INTSTAT_0 0x0198 -+#define BCMA_CORE_PCIE2_D2H_INTMASK_0 0x019c -+#define BCMA_CORE_PCIE2_LTR_STATE 0x01A0 /* Latency Tolerance Reporting */ -+#define PCIE2_LTR_ACTIVE 2 -+#define PCIE2_LTR_ACTIVE_IDLE 1 -+#define PCIE2_LTR_SLEEP 0 -+#define PCIE2_LTR_FINAL_MASK 0x300 -+#define PCIE2_LTR_FINAL_SHIFT 8 -+#define BCMA_CORE_PCIE2_PWR_INT_STATUS 0x01A4 -+#define BCMA_CORE_PCIE2_PWR_INT_MASK 0x01A8 -+#define BCMA_CORE_PCIE2_CFG_ADDR 0x01F8 -+#define BCMA_CORE_PCIE2_CFG_DATA 0x01FC -+#define BCMA_CORE_PCIE2_SYS_EQ_PAGE 0x0200 -+#define BCMA_CORE_PCIE2_SYS_MSI_PAGE 0x0204 -+#define BCMA_CORE_PCIE2_SYS_MSI_INTREN 0x0208 -+#define BCMA_CORE_PCIE2_SYS_MSI_CTRL0 0x0210 -+#define BCMA_CORE_PCIE2_SYS_MSI_CTRL1 0x0214 -+#define BCMA_CORE_PCIE2_SYS_MSI_CTRL2 0x0218 -+#define BCMA_CORE_PCIE2_SYS_MSI_CTRL3 0x021C -+#define BCMA_CORE_PCIE2_SYS_MSI_CTRL4 0x0220 -+#define BCMA_CORE_PCIE2_SYS_MSI_CTRL5 0x0224 -+#define BCMA_CORE_PCIE2_SYS_EQ_HEAD0 0x0250 -+#define BCMA_CORE_PCIE2_SYS_EQ_TAIL0 0x0254 -+#define BCMA_CORE_PCIE2_SYS_EQ_HEAD1 0x0258 -+#define BCMA_CORE_PCIE2_SYS_EQ_TAIL1 0x025C -+#define BCMA_CORE_PCIE2_SYS_EQ_HEAD2 0x0260 -+#define BCMA_CORE_PCIE2_SYS_EQ_TAIL2 0x0264 -+#define BCMA_CORE_PCIE2_SYS_EQ_HEAD3 0x0268 -+#define BCMA_CORE_PCIE2_SYS_EQ_TAIL3 0x026C -+#define BCMA_CORE_PCIE2_SYS_EQ_HEAD4 0x0270 -+#define BCMA_CORE_PCIE2_SYS_EQ_TAIL4 0x0274 -+#define BCMA_CORE_PCIE2_SYS_EQ_HEAD5 0x0278 -+#define BCMA_CORE_PCIE2_SYS_EQ_TAIL5 0x027C -+#define BCMA_CORE_PCIE2_SYS_RC_INTX_EN 0x0330 -+#define BCMA_CORE_PCIE2_SYS_RC_INTX_CSR 0x0334 -+#define BCMA_CORE_PCIE2_SYS_MSI_REQ 0x0340 -+#define BCMA_CORE_PCIE2_SYS_HOST_INTR_EN 0x0344 -+#define BCMA_CORE_PCIE2_SYS_HOST_INTR_CSR 0x0348 -+#define BCMA_CORE_PCIE2_SYS_HOST_INTR0 0x0350 -+#define BCMA_CORE_PCIE2_SYS_HOST_INTR1 0x0354 -+#define BCMA_CORE_PCIE2_SYS_HOST_INTR2 0x0358 -+#define BCMA_CORE_PCIE2_SYS_HOST_INTR3 0x035C -+#define BCMA_CORE_PCIE2_SYS_EP_INT_EN0 0x0360 -+#define BCMA_CORE_PCIE2_SYS_EP_INT_EN1 0x0364 -+#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR0 0x0370 -+#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR1 0x0374 -+#define BCMA_CORE_PCIE2_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) -+#define BCMA_CORE_PCIE2_FUNC0_IMAP0_0 0x0C00 -+#define BCMA_CORE_PCIE2_FUNC0_IMAP0_1 0x0C04 -+#define BCMA_CORE_PCIE2_FUNC0_IMAP0_2 0x0C08 -+#define BCMA_CORE_PCIE2_FUNC0_IMAP0_3 0x0C0C -+#define BCMA_CORE_PCIE2_FUNC0_IMAP0_4 0x0C10 -+#define BCMA_CORE_PCIE2_FUNC0_IMAP0_5 0x0C14 -+#define BCMA_CORE_PCIE2_FUNC0_IMAP0_6 0x0C18 -+#define BCMA_CORE_PCIE2_FUNC0_IMAP0_7 0x0C1C -+#define BCMA_CORE_PCIE2_FUNC1_IMAP0_0 0x0C20 -+#define BCMA_CORE_PCIE2_FUNC1_IMAP0_1 0x0C24 -+#define BCMA_CORE_PCIE2_FUNC1_IMAP0_2 0x0C28 -+#define BCMA_CORE_PCIE2_FUNC1_IMAP0_3 0x0C2C -+#define BCMA_CORE_PCIE2_FUNC1_IMAP0_4 0x0C30 -+#define BCMA_CORE_PCIE2_FUNC1_IMAP0_5 0x0C34 -+#define BCMA_CORE_PCIE2_FUNC1_IMAP0_6 0x0C38 -+#define BCMA_CORE_PCIE2_FUNC1_IMAP0_7 0x0C3C -+#define BCMA_CORE_PCIE2_FUNC0_IMAP1 0x0C80 -+#define BCMA_CORE_PCIE2_FUNC1_IMAP1 0x0C88 -+#define BCMA_CORE_PCIE2_FUNC0_IMAP2 0x0CC0 -+#define BCMA_CORE_PCIE2_FUNC1_IMAP2 0x0CC8 -+#define BCMA_CORE_PCIE2_IARR0_LOWER 0x0D00 -+#define BCMA_CORE_PCIE2_IARR0_UPPER 0x0D04 -+#define BCMA_CORE_PCIE2_IARR1_LOWER 0x0D08 -+#define BCMA_CORE_PCIE2_IARR1_UPPER 0x0D0C -+#define BCMA_CORE_PCIE2_IARR2_LOWER 0x0D10 -+#define BCMA_CORE_PCIE2_IARR2_UPPER 0x0D14 -+#define BCMA_CORE_PCIE2_OARR0 0x0D20 -+#define BCMA_CORE_PCIE2_OARR1 0x0D28 -+#define BCMA_CORE_PCIE2_OARR2 0x0D30 -+#define BCMA_CORE_PCIE2_OMAP0_LOWER 0x0D40 -+#define BCMA_CORE_PCIE2_OMAP0_UPPER 0x0D44 -+#define BCMA_CORE_PCIE2_OMAP1_LOWER 0x0D48 -+#define BCMA_CORE_PCIE2_OMAP1_UPPER 0x0D4C -+#define BCMA_CORE_PCIE2_OMAP2_LOWER 0x0D50 -+#define BCMA_CORE_PCIE2_OMAP2_UPPER 0x0D54 -+#define BCMA_CORE_PCIE2_FUNC1_IARR1_SIZE 0x0D58 -+#define BCMA_CORE_PCIE2_FUNC1_IARR2_SIZE 0x0D5C -+#define BCMA_CORE_PCIE2_MEM_CONTROL 0x0F00 -+#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG0 0x0F04 -+#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG1 0x0F08 -+#define BCMA_CORE_PCIE2_LINK_STATUS 0x0F0C -+#define BCMA_CORE_PCIE2_STRAP_STATUS 0x0F10 -+#define BCMA_CORE_PCIE2_RESET_STATUS 0x0F14 -+#define BCMA_CORE_PCIE2_RESETEN_IN_LINKDOWN 0x0F18 -+#define BCMA_CORE_PCIE2_MISC_INTR_EN 0x0F1C -+#define BCMA_CORE_PCIE2_TX_DEBUG_CFG 0x0F20 -+#define BCMA_CORE_PCIE2_MISC_CONFIG 0x0F24 -+#define BCMA_CORE_PCIE2_MISC_STATUS 0x0F28 -+#define BCMA_CORE_PCIE2_INTR_EN 0x0F30 -+#define BCMA_CORE_PCIE2_INTR_CLEAR 0x0F34 -+#define BCMA_CORE_PCIE2_INTR_STATUS 0x0F38 -+ -+/* PCIE gen2 config regs */ -+#define PCIE2_INTSTATUS 0x090 -+#define PCIE2_INTMASK 0x094 -+#define PCIE2_SBMBX 0x098 -+ -+#define PCIE2_PMCR_REFUP 0x1814 /* Trefup time */ -+ -+#define PCIE2_CAP_DEVSTSCTRL2_OFFSET 0xD4 -+#define PCIE2_CAP_DEVSTSCTRL2_LTRENAB 0x400 -+#define PCIE2_PVT_REG_PM_CLK_PERIOD 0x184c -+ -+struct bcma_drv_pcie2 { -+ struct bcma_device *core; -+}; -+ -+#define pcie2_read16(pcie2, offset) bcma_read16((pcie2)->core, offset) -+#define pcie2_read32(pcie2, offset) bcma_read32((pcie2)->core, offset) -+#define pcie2_write16(pcie2, offset, val) bcma_write16((pcie2)->core, offset, val) -+#define pcie2_write32(pcie2, offset, val) bcma_write32((pcie2)->core, offset, val) -+ -+#define pcie2_set32(pcie2, offset, set) bcma_set32((pcie2)->core, offset, set) -+#define pcie2_mask32(pcie2, offset, mask) bcma_mask32((pcie2)->core, offset, mask) -+ -+void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2); -+ -+#endif /* LINUX_BCMA_DRIVER_PCIE2_H_ */ ---- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c -+++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c -@@ -679,27 +679,6 @@ bool ai_clkctl_cc(struct si_pub *sih, en - return mode == BCMA_CLKMODE_FAST; - } - --void ai_pci_up(struct si_pub *sih) --{ -- struct si_info *sii; -- -- sii = container_of(sih, struct si_info, pub); -- -- if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI) -- bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true); --} -- --/* Unconfigure and/or apply various WARs when going down */ --void ai_pci_down(struct si_pub *sih) --{ -- struct si_info *sii; -- -- sii = container_of(sih, struct si_info, pub); -- -- if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI) -- bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false); --} -- - /* Enable BT-COEX & Ex-PA for 4313 */ - void ai_epa_4313war(struct si_pub *sih) - { ---- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h -+++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h -@@ -183,9 +183,6 @@ extern u16 ai_clkctl_fast_pwrup_delay(st - extern bool ai_clkctl_cc(struct si_pub *sih, enum bcma_clkmode mode); - extern bool ai_deviceremoved(struct si_pub *sih); - --extern void ai_pci_down(struct si_pub *sih); --extern void ai_pci_up(struct si_pub *sih); -- - /* Enable Ex-PA for 4313 */ - extern void ai_epa_4313war(struct si_pub *sih); - ---- a/drivers/net/wireless/brcm80211/brcmsmac/main.c -+++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c -@@ -4667,7 +4667,7 @@ static int brcms_b_attach(struct brcms_c - brcms_c_coredisable(wlc_hw); - - /* Match driver "down" state */ -- ai_pci_down(wlc_hw->sih); -+ bcma_core_pci_down(wlc_hw->d11core->bus); - - /* turn off pll and xtal to match driver "down" state */ - brcms_b_xtal(wlc_hw, OFF); -@@ -5010,12 +5010,12 @@ static int brcms_b_up_prep(struct brcms_ - */ - if (brcms_b_radio_read_hwdisabled(wlc_hw)) { - /* put SB PCI in down state again */ -- ai_pci_down(wlc_hw->sih); -+ bcma_core_pci_down(wlc_hw->d11core->bus); - brcms_b_xtal(wlc_hw, OFF); - return -ENOMEDIUM; - } - -- ai_pci_up(wlc_hw->sih); -+ bcma_core_pci_up(wlc_hw->d11core->bus); - - /* reset the d11 core */ - brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS); -@@ -5212,7 +5212,7 @@ static int brcms_b_down_finish(struct br - - /* turn off primary xtal and pll */ - if (!wlc_hw->noreset) { -- ai_pci_down(wlc_hw->sih); -+ bcma_core_pci_down(wlc_hw->d11core->bus); - brcms_b_xtal(wlc_hw, OFF); - } - } |