summaryrefslogtreecommitdiff
path: root/target/linux/brcm63xx/patches-3.6/426-SPI-MIPS-BCM63XX-Add-HS-SPI-driver.patch
blob: 2b213968a112fafce7773d4ddc9429016d1bfbd6 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
From 4b27423676485d05bcd6fc6f3809164fb8f9d22d Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jonas.gorski@gmail.com>
Date: Sat, 12 Nov 2011 12:19:55 +0100
Subject: [PATCH 30/60] SPI: MIPS: BCM63XX: Add HSSPI driver

Add a driver for the High Speed SPI controller found on newer BCM63XX SoCs.

Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
---
 .../include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h   |    2 +
 drivers/spi/Kconfig                                |    7 +
 drivers/spi/Makefile                               |    1 +
 drivers/spi/spi-bcm63xx-hsspi.c                    |  427 ++++++++++++++++++++
 4 files changed, 437 insertions(+), 0 deletions(-)
 create mode 100644 drivers/spi/spi-bcm63xx-hsspi.c

--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h
@@ -17,4 +17,6 @@ struct bcm63xx_hsspi_pdata {
 
 #define HSSPI_PLL_HZ_6328	133333333
 
+#define HSSPI_BUFFER_LEN   	512
+
 #endif /* BCM63XX_DEV_HSSPI_H */
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -100,6 +100,13 @@ config SPI_BCM63XX
 	help
           Enable support for the SPI controller on the Broadcom BCM63xx SoCs.
 
+config SPI_BCM63XX_HSSPI
+	tristate "Broadcom BCM63XX HS SPI controller driver"
+	depends on BCM63XX
+	help
+	  This enables support for the High Speed SPI controller present on
+	  newer Broadcom BCM63XX SoCs.
+
 config SPI_BITBANG
 	tristate "Utilities for Bitbanging SPI masters"
 	help
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_SPI_ATMEL)			+= spi-atmel.o
 obj-$(CONFIG_SPI_ATH79)			+= spi-ath79.o
 obj-$(CONFIG_SPI_AU1550)		+= spi-au1550.o
 obj-$(CONFIG_SPI_BCM63XX)		+= spi-bcm63xx.o
+obj-$(CONFIG_SPI_BCM63XX_HSSPI)		+= spi-bcm63xx-hsspi.o
 obj-$(CONFIG_SPI_BFIN5XX)		+= spi-bfin5xx.o
 obj-$(CONFIG_SPI_BFIN_SPORT)		+= spi-bfin-sport.o
 obj-$(CONFIG_SPI_BITBANG)		+= spi-bitbang.o
--- /dev/null
+++ b/drivers/spi/spi-bcm63xx-hsspi.c
@@ -0,0 +1,427 @@
+/*
+ * Broadcom BCM63XX High Speed SPI Controller driver
+ *
+ * Copyright 2000-2010 Broadcom Corporation
+ * Copyright 2012 Jonas Gorski <jonas.gorski@gmail.com>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/spi/spi.h>
+#include <linux/workqueue.h>
+
+#include <bcm63xx_regs.h>
+#include <bcm63xx_dev_hsspi.h>
+
+#define HSSPI_OP_CODE_SHIFT	13
+#define HSSPI_OP_SLEEP		(0 << HSSPI_OP_CODE_SHIFT)
+#define HSSPI_OP_READ_WRITE	(1 << HSSPI_OP_CODE_SHIFT)
+#define HSSPI_OP_WRITE		(2 << HSSPI_OP_CODE_SHIFT)
+#define HSSPI_OP_READ		(3 << HSSPI_OP_CODE_SHIFT)
+
+#define HSSPI_MAX_PREPEND_LEN	15
+
+#define HSSPI_MAX_SYNC_CLOCK	30000000
+
+struct bcm63xx_hsspi {
+	struct completion	done;
+	struct spi_transfer	*curr_trans;
+
+	struct platform_device  *pdev;
+	struct clk		*clk;
+	void __iomem		*regs;
+	u8 __iomem		*fifo;
+
+	u32			speed_hz;
+	int			irq;
+};
+
+static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs, int hz,
+				  int profile)
+{
+	u32 reg;
+
+	reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
+	bcm_hsspi_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg,
+			 HSSPI_PROFILE_CLK_CTRL_REG(profile));
+
+	reg = bcm_hsspi_readl(HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
+	if (hz > HSSPI_MAX_SYNC_CLOCK)
+		reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH;
+	else
+		reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH;
+	bcm_hsspi_writel(reg, HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
+}
+
+static int bcm63xx_hsspi_do_txrx(struct spi_device *spi,
+				 struct spi_transfer *t1,
+				 struct spi_transfer *t2)
+{
+	struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
+	u8 chip_select = spi->chip_select;
+	u16 opcode = 0;
+	int len, prepend_size = 0;
+
+	init_completion(&bs->done);
+
+	bs->curr_trans = t2 ? t2 : t1;
+	bcm63xx_hsspi_set_clk(bs, bs->curr_trans->speed_hz, chip_select);
+
+	if (t2 && !t2->tx_buf)
+		prepend_size = t1->len;
+
+	bcm_hsspi_writel(prepend_size << MODE_CTRL_PREPENDBYTE_CNT_SHIFT |
+			 2 << MODE_CTRL_MULTIDATA_WR_STRT_SHIFT |
+			 2 << MODE_CTRL_MULTIDATA_RD_STRT_SHIFT | 0xff,
+			 HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
+
+	if (t1->rx_buf && t1->tx_buf)
+		opcode = HSSPI_OP_READ_WRITE;
+	else if (t1->rx_buf || (t2 && t2->rx_buf))
+		opcode = HSSPI_OP_READ;
+	else if (t1->tx_buf)
+		opcode = HSSPI_OP_WRITE;
+
+	if (opcode == HSSPI_OP_READ && t2)
+		len = t2->len;
+	else
+		len = t1->len;
+
+	if (t1->tx_buf) {
+		memcpy_toio(bs->fifo + 2, t1->tx_buf, t1->len);
+		if (t2 && t2->tx_buf) {
+			memcpy_toio(bs->fifo + 2 + t1->len,
+				    t2->tx_buf, t2->len);
+			len += t2->len;
+		}
+	}
+
+	opcode |= len;
+	memcpy_toio(bs->fifo, &opcode, sizeof(opcode));
+
+	/* enable interrupt */
+	bcm_hsspi_writel(HSSPI_PING0_CMD_DONE, HSSPI_INT_MASK_REG);
+
+	/* start the transfer */
+	bcm_hsspi_writel(chip_select << PINGPONG_CMD_SS_SHIFT |
+			 chip_select << PINGPONG_CMD_PROFILE_SHIFT |
+			 PINGPONG_COMMAND_START_NOW,
+			 HSSPI_PINGPONG_COMMAND_REG(0));
+
+	if (wait_for_completion_timeout(&bs->done, HZ) == 0) {
+		dev_err(&bs->pdev->dev, "transfer timed out!\n");
+		return -ETIMEDOUT;
+	}
+
+	return t1->len + (t2 ? t2->len : 0);
+}
+
+static int bcm63xx_hsspi_setup(struct spi_device *spi)
+{
+	u32 reg;
+
+	if (spi->bits_per_word != 8)
+		return -EINVAL;
+
+	if (spi->max_speed_hz == 0)
+		return -EINVAL;
+
+	reg = bcm_hsspi_readl(HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
+	reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
+	if (spi->mode & SPI_CPHA)
+		reg |= SIGNAL_CTRL_LAUNCH_RISING;
+	else
+		reg |= SIGNAL_CTRL_LATCH_RISING;
+	bcm_hsspi_writel(reg, HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
+
+	return 0;
+}
+
+static int bcm63xx_hsspi_transfer_one(struct spi_master *master,
+				      struct spi_message *msg)
+{
+	struct spi_transfer *t, *prev = NULL;
+	struct spi_device *spi = msg->spi;
+	u32 reg;
+	int ret = -EINVAL;
+	int len = 0;
+
+	/* check if we are able to make these transfers */
+	list_for_each_entry(t, &msg->transfers, transfer_list) {
+		if (!t->tx_buf && !t->rx_buf)
+			goto out;
+
+		if (t->speed_hz == 0)
+			t->speed_hz = spi->max_speed_hz;
+
+		if (t->speed_hz > spi->max_speed_hz)
+			goto out;
+
+		if (t->len > HSSPI_BUFFER_LEN)
+			goto out;
+
+		/*
+		 * This controller does not support keeping the chip select
+		 * active between transfers.
+		 * This logic currently supports combining:
+		 *  write then read with no cs_change (e.g. m25p80 RDSR)
+		 *  write then write with no cs_change (e.g. m25p80 PP)
+		 */
+		if (prev && prev->tx_buf && !prev->cs_change && !t->cs_change) {
+			/*
+			 * reject if we have to combine two tx transfers and
+			 * their combined length is bigger than the buffer
+			 */
+			if (prev->tx_buf && t->tx_buf &&
+			    (prev->len + t->len) > HSSPI_BUFFER_LEN)
+				goto out;
+			/*
+			 * reject if we need write more than 15 bytes in read
+			 * then write.
+			 */
+			if (prev->tx_buf && t->rx_buf &&
+			    prev->len > HSSPI_MAX_PREPEND_LEN)
+				goto out;
+		}
+
+	}
+
+	/* setup clock polarity */
+	reg = bcm_hsspi_readl(HSSPI_GLOBAL_CTRL_REG);
+	reg &= ~GLOBAL_CTRL_CLK_POLARITY;
+	if (spi->mode & SPI_CPOL)
+		reg |= GLOBAL_CTRL_CLK_POLARITY;
+	bcm_hsspi_writel(reg, HSSPI_GLOBAL_CTRL_REG);
+
+	list_for_each_entry(t, &msg->transfers, transfer_list) {
+		if (prev && prev->tx_buf && !prev->cs_change && !t->cs_change) {
+			/* combine write with following transfer */
+			ret = bcm63xx_hsspi_do_txrx(msg->spi, prev, t);
+			if (ret < 0)
+				goto out;
+
+			len += ret;
+			prev = NULL;
+			continue;
+		}
+
+		/* write the previous pending transfer */
+		if (prev != NULL) {
+			ret = bcm63xx_hsspi_do_txrx(msg->spi, prev, NULL);
+			if (ret < 0)
+				goto out;
+
+			len += ret;
+		}
+
+		prev = t;
+	}
+
+	/* do last pending transfer */
+	if (prev != NULL) {
+		ret = bcm63xx_hsspi_do_txrx(msg->spi, prev, NULL);
+		if (ret < 0)
+			goto out;
+		len += ret;
+	}
+
+	msg->actual_length = len;
+	ret = 0;
+out:
+	msg->status = ret;
+	spi_finalize_current_message(master);
+	return 0;
+}
+
+static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id)
+{
+	struct spi_master *master = (struct spi_master *)dev_id;
+	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
+
+	if (bcm_hsspi_readl(HSSPI_INT_STATUS_MASKED_REG) == 0)
+		return IRQ_NONE;
+
+	bcm_hsspi_writel(HSSPI_INT_CLEAR_ALL, HSSPI_INT_STATUS_REG);
+	bcm_hsspi_writel(0, HSSPI_INT_MASK_REG);
+
+	if (bs->curr_trans && bs->curr_trans->rx_buf)
+		memcpy_fromio(bs->curr_trans->rx_buf,  bs->fifo,
+			      bs->curr_trans->len);
+	complete(&bs->done);
+
+	return IRQ_HANDLED;
+}
+
+static int __devinit bcm63xx_hsspi_probe(struct platform_device *pdev)
+{
+
+	struct spi_master *master;
+	struct bcm63xx_hsspi *bs;
+	struct resource *res_mem;
+	void __iomem *regs;
+	struct device *dev = &pdev->dev;
+	struct bcm63xx_hsspi_pdata *pdata = pdev->dev.platform_data;
+	struct clk *clk;
+	int irq;
+	int ret;
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(dev, "no irq\n");
+		return -ENXIO;
+	}
+
+	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	regs = devm_request_and_ioremap(dev, res_mem);
+	if (!regs) {
+		dev_err(dev, "unable to ioremap regs\n");
+		return -ENXIO;
+	}
+
+	clk = clk_get(dev, "hsspi");
+
+	if (IS_ERR(clk)) {
+		ret = PTR_ERR(clk);
+		goto out_release;
+	}
+
+	clk_prepare_enable(clk);
+
+	master = spi_alloc_master(&pdev->dev, sizeof(*bs));
+	if (!master) {
+		ret = -ENOMEM;
+		goto out_disable_clk;
+	}
+
+	bs = spi_master_get_devdata(master);
+	bs->pdev = pdev;
+	bs->clk = clk;
+	bs->regs = regs;
+
+	master->bus_num = pdata->bus_num;
+	master->num_chipselect = 8;
+	master->setup = bcm63xx_hsspi_setup;
+	master->transfer_one_message = bcm63xx_hsspi_transfer_one;
+	master->mode_bits = SPI_CPOL | SPI_CPHA;
+
+	bs->speed_hz = pdata->speed_hz;
+	bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0));
+
+	platform_set_drvdata(pdev, master);
+
+	bs->curr_trans = NULL;
+
+	/* Initialize the hardware */
+	bcm_hsspi_writel(0, HSSPI_INT_MASK_REG);
+
+	/* clean up any pending interrupts */
+	bcm_hsspi_writel(HSSPI_INT_CLEAR_ALL, HSSPI_INT_STATUS_REG);
+
+	bcm_hsspi_writel(bcm_hsspi_readl(HSSPI_GLOBAL_CTRL_REG) |
+			 GLOBAL_CTRL_CLK_GATE_SSOFF,
+			 HSSPI_GLOBAL_CTRL_REG);
+
+	ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED,
+			       pdev->name, master);
+
+	if (ret)
+		goto out_put_master;
+
+	/* register and we are done */
+	ret = spi_register_master(master);
+	if (ret)
+		goto out_free_irq;
+
+	return 0;
+
+out_free_irq:
+	devm_free_irq(dev, bs->irq, master);
+out_put_master:
+	spi_master_put(master);
+out_disable_clk:
+	clk_disable_unprepare(clk);
+	clk_put(clk);
+out_release:
+	devm_ioremap_release(dev, regs);
+
+	return ret;
+}
+
+
+static int __exit bcm63xx_hsspi_remove(struct platform_device *pdev)
+{
+	struct spi_master *master = platform_get_drvdata(pdev);
+	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
+
+	spi_unregister_master(master);
+
+	/* reset the hardware and block queue progress */
+	bcm_hsspi_writel(0, HSSPI_INT_MASK_REG);
+	clk_disable_unprepare(bs->clk);
+	clk_put(bs->clk);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int bcm63xx_hsspi_suspend(struct platform_device *pdev,
+				 pm_message_t mesg)
+{
+	struct spi_master *master = platform_get_drvdata(pdev);
+	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
+
+	spi_master_suspend(master);
+	clk_disable(bs->clk);
+
+	return 0;
+}
+
+static int bcm63xx_hsspi_resume(struct platform_device *pdev)
+{
+	struct spi_master *master = platform_get_drvdata(pdev);
+	struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
+
+	clk_enable(bs->clk);
+	spi_master_resume(master);
+
+	return 0;
+}
+
+static const struct dev_pm_ops bcm63xx_hsspi_pm_ops = {
+	.suspend	= bcm63xx_hsspi_suspend,
+	.resume		= bcm63xx_hsspi_resume,
+};
+
+#define BCM63XX_HSSPI_PM_OPS	(&bcm63xx_hsspi_pm_ops)
+#else
+#define BCM63XX_HSSPI_PM_OPS	NULL
+#endif
+
+
+
+static struct platform_driver bcm63xx_hsspi_driver = {
+	.driver = {
+		.name	= "bcm63xx-hsspi",
+		.owner	= THIS_MODULE,
+		.pm	= BCM63XX_HSSPI_PM_OPS,
+	},
+	.probe		= bcm63xx_hsspi_probe,
+	.remove		= __exit_p(bcm63xx_hsspi_remove),
+};
+
+module_platform_driver(bcm63xx_hsspi_driver);
+
+MODULE_ALIAS("platform:bcm63xx_hsspi");
+MODULE_DESCRIPTION("Broadcom BCM63xx HS SPI Controller driver");
+MODULE_AUTHOR("Jonas Gorski <jonas.gorski@gmail.com>");
+MODULE_LICENSE("GPL");