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authorJohn Crispin <john@openwrt.org>2011-07-19 18:06:42 +0000
committerJohn Crispin <john@openwrt.org>2011-07-19 18:06:42 +0000
commit78a9b1a2ade2329658302da89ac052f1d5d8e4b4 (patch)
tree3c5123f9c009ee43e2eccba67be820232025c6b2
parent3833b7be24ba9f8cb847de8197e60147068afe67 (diff)
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fixes pci on lantiq AR9 SoC
SVN-Revision: 27695
-rw-r--r--target/linux/lantiq/patches-2.6.39/999-fix_pci.patch18
1 files changed, 18 insertions, 0 deletions
diff --git a/target/linux/lantiq/patches-2.6.39/999-fix_pci.patch b/target/linux/lantiq/patches-2.6.39/999-fix_pci.patch
new file mode 100644
index 0000000..94a3bc7
--- /dev/null
+++ b/target/linux/lantiq/patches-2.6.39/999-fix_pci.patch
@@ -0,0 +1,18 @@
+--- a/arch/mips/pci/pci-lantiq.c
++++ b/arch/mips/pci/pci-lantiq.c
+@@ -171,8 +171,13 @@
+ u32 temp_buffer;
+
+ /* set clock to 33Mhz */
+- ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR);
+- ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR);
++ if (ltq_is_ar9()) {
++ ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0x1f00000, LTQ_CGU_IFCCR);
++ ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0xe00000, LTQ_CGU_IFCCR);
++ } else {
++ ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR);
++ ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR);
++ }
+
+ /* external or internal clock ? */
+ if (conf->clock) {